[Sparc] Remove custom lowering for ADD[CE] / SUB[CE] #100861
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The default lowering produces fewer instructions.
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@llvm/pr-subscribers-backend-sparc Author: Sergei Barannikov (s-barannikov) ChangesThe default lowering produces fewer instructions. Patch is 39.52 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/100861.diff 5 Files Affected:
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index 50aa19446f880..41aa2dcffe28a 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -1731,16 +1731,12 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
- setOperationAction(ISD::ADDC, MVT::i32, Custom);
- setOperationAction(ISD::ADDE, MVT::i32, Custom);
- setOperationAction(ISD::SUBC, MVT::i32, Custom);
- setOperationAction(ISD::SUBE, MVT::i32, Custom);
+ setOperationAction(ISD::ADDC, MVT::i32, Legal);
+ setOperationAction(ISD::ADDE, MVT::i32, Legal);
+ setOperationAction(ISD::SUBC, MVT::i32, Legal);
+ setOperationAction(ISD::SUBE, MVT::i32, Legal);
if (Subtarget->is64Bit()) {
- setOperationAction(ISD::ADDC, MVT::i64, Custom);
- setOperationAction(ISD::ADDE, MVT::i64, Custom);
- setOperationAction(ISD::SUBC, MVT::i64, Custom);
- setOperationAction(ISD::SUBE, MVT::i64, Custom);
setOperationAction(ISD::BITCAST, MVT::f64, Expand);
setOperationAction(ISD::BITCAST, MVT::i64, Expand);
setOperationAction(ISD::SELECT, MVT::i64, Expand);
@@ -3105,55 +3101,6 @@ static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
return DstReg128;
}
-static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
-
- if (Op.getValueType() != MVT::i64)
- return Op;
-
- SDLoc dl(Op);
- SDValue Src1 = Op.getOperand(0);
- SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1);
- SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1,
- DAG.getConstant(32, dl, MVT::i64));
- Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi);
-
- SDValue Src2 = Op.getOperand(1);
- SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2);
- SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2,
- DAG.getConstant(32, dl, MVT::i64));
- Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi);
-
-
- bool hasChain = false;
- unsigned hiOpc = Op.getOpcode();
- switch (Op.getOpcode()) {
- default: llvm_unreachable("Invalid opcode");
- case ISD::ADDC: hiOpc = ISD::ADDE; break;
- case ISD::ADDE: hasChain = true; break;
- case ISD::SUBC: hiOpc = ISD::SUBE; break;
- case ISD::SUBE: hasChain = true; break;
- }
- SDValue Lo;
- SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Glue);
- if (hasChain) {
- Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo,
- Op.getOperand(2));
- } else {
- Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo);
- }
- SDValue Hi = DAG.getNode(hiOpc, dl, VTs, Src1Hi, Src2Hi, Lo.getValue(1));
- SDValue Carry = Hi.getValue(1);
-
- Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo);
- Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi);
- Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi,
- DAG.getConstant(32, dl, MVT::i64));
-
- SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo);
- SDValue Ops[2] = { Dst, Carry };
- return DAG.getMergeValues(Ops, dl);
-}
-
// Custom lower UMULO/SMULO for SPARC. This code is similar to ExpandNode()
// in LegalizeDAG.cpp except the order of arguments to the library function.
static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG,
@@ -3283,10 +3230,6 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9);
case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this);
case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this);
- case ISD::ADDC:
- case ISD::ADDE:
- case ISD::SUBC:
- case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
case ISD::UMULO:
case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this);
case ISD::ATOMIC_LOAD:
diff --git a/llvm/test/CodeGen/SPARC/2011-01-11-CC.ll b/llvm/test/CodeGen/SPARC/2011-01-11-CC.ll
index c7bf71bb06c5b..62cf06d7ee3c8 100644
--- a/llvm/test/CodeGen/SPARC/2011-01-11-CC.ll
+++ b/llvm/test/CodeGen/SPARC/2011-01-11-CC.ll
@@ -1,128 +1,459 @@
-; RUN: llc -march=sparc <%s | FileCheck %s -check-prefix=V8
-; RUN: llc -march=sparc -mattr=v9 <%s | FileCheck %s -check-prefix=V9
-; RUN: llc -mtriple=sparc64-unknown-linux <%s | FileCheck %s -check-prefix=SPARC64
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -march=sparc %s -o - | FileCheck %s -check-prefix=V8
+; RUN: llc -march=sparc -mattr=v9 %s -o - | FileCheck %s -check-prefix=V9
+; RUN: llc -mtriple=sparc64-unknown-linux %s -o - | FileCheck %s -check-prefix=SPARC64
-
-define i32 @test_addx(i64 %a, i64 %b, i64 %c) nounwind readnone noinline {
+define i32 @test_addx(i64 %a, i64 %b, i64 %c) nounwind {
+; V8-LABEL: test_addx:
+; V8: ! %bb.0: ! %entry
+; V8-NEXT: addcc %o1, %o3, %o3
+; V8-NEXT: addxcc %o0, %o2, %o1
+; V8-NEXT: mov 1, %o0
+; V8-NEXT: cmp %o1, %o4
+; V8-NEXT: bleu .LBB0_4
+; V8-NEXT: mov %o0, %o2
+; V8-NEXT: ! %bb.1: ! %entry
+; V8-NEXT: cmp %o3, %o5
+; V8-NEXT: bleu .LBB0_5
+; V8-NEXT: nop
+; V8-NEXT: .LBB0_2: ! %entry
+; V8-NEXT: cmp %o1, %o4
+; V8-NEXT: bne .LBB0_6
+; V8-NEXT: nop
+; V8-NEXT: .LBB0_3: ! %entry
+; V8-NEXT: retl
+; V8-NEXT: nop
+; V8-NEXT: .LBB0_4: ! %entry
+; V8-NEXT: mov %g0, %o2
+; V8-NEXT: cmp %o3, %o5
+; V8-NEXT: bgu .LBB0_2
+; V8-NEXT: nop
+; V8-NEXT: .LBB0_5: ! %entry
+; V8-NEXT: mov %g0, %o0
+; V8-NEXT: cmp %o1, %o4
+; V8-NEXT: be .LBB0_3
+; V8-NEXT: nop
+; V8-NEXT: .LBB0_6: ! %entry
+; V8-NEXT: retl
+; V8-NEXT: mov %o2, %o0
+;
+; V9-LABEL: test_addx:
+; V9: ! %bb.0: ! %entry
+; V9-NEXT: mov %g0, %g2
+; V9-NEXT: mov %g0, %g3
+; V9-NEXT: addcc %o1, %o3, %o1
+; V9-NEXT: addxcc %o0, %o2, %o0
+; V9-NEXT: cmp %o0, %o4
+; V9-NEXT: movgu %icc, 1, %g2
+; V9-NEXT: cmp %o1, %o5
+; V9-NEXT: movgu %icc, 1, %g3
+; V9-NEXT: cmp %o0, %o4
+; V9-NEXT: move %icc, %g3, %g2
+; V9-NEXT: retl
+; V9-NEXT: mov %g2, %o0
+;
+; SPARC64-LABEL: test_addx:
+; SPARC64: ! %bb.0: ! %entry
+; SPARC64-NEXT: mov %g0, %o3
+; SPARC64-NEXT: add %o0, %o1, %o0
+; SPARC64-NEXT: cmp %o0, %o2
+; SPARC64-NEXT: movgu %xcc, 1, %o3
+; SPARC64-NEXT: retl
+; SPARC64-NEXT: srl %o3, 0, %o0
entry:
-; V8: addcc
-; V8-NOT: subcc
-; V8: addx
-; V9: addcc
-; V9-NOT: subcc
-; V9: addx
-; V9: mov{{e|ne}} %icc
%0 = add i64 %a, %b
%1 = icmp ugt i64 %0, %c
%2 = zext i1 %1 to i32
ret i32 %2
}
-
-define i32 @test_select_int_icc(i32 %a, i32 %b, i32 %c) nounwind readnone noinline {
+define i32 @test_select_int_icc(i32 %a, i32 %b, i32 %c) nounwind {
+; V8-LABEL: test_select_int_icc:
+; V8: ! %bb.0: ! %entry
+; V8-NEXT: cmp %o0, 0
+; V8-NEXT: be .LBB1_2
+; V8-NEXT: mov %o1, %o0
+; V8-NEXT: ! %bb.1: ! %entry
+; V8-NEXT: mov %o2, %o0
+; V8-NEXT: .LBB1_2: ! %entry
+; V8-NEXT: retl
+; V8-NEXT: nop
+;
+; V9-LABEL: test_select_int_icc:
+; V9: ! %bb.0: ! %entry
+; V9-NEXT: cmp %o0, 0
+; V9-NEXT: move %icc, %o1, %o2
+; V9-NEXT: retl
+; V9-NEXT: mov %o2, %o0
+;
+; SPARC64-LABEL: test_select_int_icc:
+; SPARC64: ! %bb.0: ! %entry
+; SPARC64-NEXT: cmp %o0, 0
+; SPARC64-NEXT: move %icc, %o1, %o2
+; SPARC64-NEXT: retl
+; SPARC64-NEXT: mov %o2, %o0
entry:
-; V8: test_select_int_icc
-; V8: cmp
-; V8: {{be|bne}}
-; V9: test_select_int_icc
-; V9: cmp
-; V9-NOT: {{be|bne}}
-; V9: mov{{e|ne}} %icc
%0 = icmp eq i32 %a, 0
%1 = select i1 %0, i32 %b, i32 %c
ret i32 %1
}
-
-define float @test_select_fp_icc(i32 %a, float %f1, float %f2) nounwind readnone noinline {
+define float @test_select_fp_icc(i32 %a, float %f1, float %f2) nounwind {
+; V8-LABEL: test_select_fp_icc:
+; V8: ! %bb.0: ! %entry
+; V8-NEXT: add %sp, -104, %sp
+; V8-NEXT: st %o2, [%sp+100]
+; V8-NEXT: cmp %o0, 0
+; V8-NEXT: be .LBB2_2
+; V8-NEXT: st %o1, [%sp+96]
+; V8-NEXT: ! %bb.1: ! %entry
+; V8-NEXT: ld [%sp+100], %f0
+; V8-NEXT: retl
+; V8-NEXT: add %sp, 104, %sp
+; V8-NEXT: .LBB2_2:
+; V8-NEXT: ld [%sp+96], %f0
+; V8-NEXT: retl
+; V8-NEXT: add %sp, 104, %sp
+;
+; V9-LABEL: test_select_fp_icc:
+; V9: ! %bb.0: ! %entry
+; V9-NEXT: add %sp, -104, %sp
+; V9-NEXT: st %o2, [%sp+100]
+; V9-NEXT: st %o1, [%sp+96]
+; V9-NEXT: ld [%sp+100], %f0
+; V9-NEXT: ld [%sp+96], %f1
+; V9-NEXT: cmp %o0, 0
+; V9-NEXT: fmovse %icc, %f1, %f0
+; V9-NEXT: retl
+; V9-NEXT: add %sp, 104, %sp
+;
+; SPARC64-LABEL: test_select_fp_icc:
+; SPARC64: ! %bb.0: ! %entry
+; SPARC64-NEXT: fmovs %f5, %f0
+; SPARC64-NEXT: cmp %o0, 0
+; SPARC64-NEXT: retl
+; SPARC64-NEXT: fmovse %icc, %f3, %f0
entry:
-; V8: test_select_fp_icc
-; V8: cmp
-; V8: {{be|bne}}
-; V9: test_select_fp_icc
-; V9: cmp
-; V9-NOT: {{be|bne}}
-; V9: fmovs{{e|ne}} %icc
%0 = icmp eq i32 %a, 0
%1 = select i1 %0, float %f1, float %f2
ret float %1
}
-define double @test_select_dfp_icc(i32 %a, double %f1, double %f2) nounwind readnone noinline {
+define double @test_select_dfp_icc(i32 %a, double %f1, double %f2) nounwind {
+; V8-LABEL: test_select_dfp_icc:
+; V8: ! %bb.0: ! %entry
+; V8-NEXT: add %sp, -112, %sp
+; V8-NEXT: mov %o4, %o5
+; V8-NEXT: mov %o2, %g3
+; V8-NEXT: mov %o3, %o4
+; V8-NEXT: std %o4, [%sp+96]
+; V8-NEXT: cmp %o0, 0
+; V8-NEXT: mov %o1, %g2
+; V8-NEXT: be .LBB3_2
+; V8-NEXT: std %g2, [%sp+104]
+; V8-NEXT: ! %bb.1: ! %entry
+; V8-NEXT: ldd [%sp+96], %f0
+; V8-NEXT: retl
+; V8-NEXT: add %sp, 112, %sp
+; V8-NEXT: .LBB3_2:
+; V8-NEXT: ldd [%sp+104], %f0
+; V8-NEXT: retl
+; V8-NEXT: add %sp, 112, %sp
+;
+; V9-LABEL: test_select_dfp_icc:
+; V9: ! %bb.0: ! %entry
+; V9-NEXT: add %sp, -112, %sp
+; V9-NEXT: mov %o4, %o5
+; V9-NEXT: mov %o2, %g3
+; V9-NEXT: mov %o3, %o4
+; V9-NEXT: std %o4, [%sp+96]
+; V9-NEXT: mov %o1, %g2
+; V9-NEXT: std %g2, [%sp+104]
+; V9-NEXT: ldd [%sp+96], %f0
+; V9-NEXT: ldd [%sp+104], %f2
+; V9-NEXT: cmp %o0, 0
+; V9-NEXT: fmovde %icc, %f2, %f0
+; V9-NEXT: retl
+; V9-NEXT: add %sp, 112, %sp
+;
+; SPARC64-LABEL: test_select_dfp_icc:
+; SPARC64: ! %bb.0: ! %entry
+; SPARC64-NEXT: fmovd %f4, %f0
+; SPARC64-NEXT: cmp %o0, 0
+; SPARC64-NEXT: retl
+; SPARC64-NEXT: fmovde %icc, %f2, %f0
entry:
-; V8: test_select_dfp_icc
-; V8: cmp
-; V8: {{be|bne}}
-; V9: test_select_dfp_icc
-; V9: cmp
-; V9-NOT: {{be|bne}}
-; V9: fmovd{{e|ne}} %icc
%0 = icmp eq i32 %a, 0
%1 = select i1 %0, double %f1, double %f2
ret double %1
}
-define i32 @test_select_int_fcc(float %f, i32 %a, i32 %b) nounwind readnone noinline {
+define i32 @test_select_int_fcc(float %f, i32 %a, i32 %b) nounwind {
+; V8-LABEL: test_select_int_fcc:
+; V8: ! %bb.0: ! %entry
+; V8-NEXT: add %sp, -96, %sp
+; V8-NEXT: st %o0, [%sp+92]
+; V8-NEXT: ld [%sp+92], %f0
+; V8-NEXT: sethi %hi(.LCPI4_0), %o0
+; V8-NEXT: ld [%o0+%lo(.LCPI4_0)], %f1
+; V8-NEXT: fcmps %f0, %f1
+; V8-NEXT: nop
+; V8-NEXT: fbne .LBB4_2
+; V8-NEXT: mov %o1, %o0
+; V8-NEXT: ! %bb.1: ! %entry
+; V8-NEXT: mov %o2, %o0
+; V8-NEXT: .LBB4_2: ! %entry
+; V8-NEXT: retl
+; V8-NEXT: add %sp, 96, %sp
+;
+; V9-LABEL: test_select_int_fcc:
+; V9: ! %bb.0: ! %entry
+; V9-NEXT: add %sp, -96, %sp
+; V9-NEXT: st %o0, [%sp+92]
+; V9-NEXT: ld [%sp+92], %f0
+; V9-NEXT: sethi %hi(.LCPI4_0), %o0
+; V9-NEXT: ld [%o0+%lo(.LCPI4_0)], %f1
+; V9-NEXT: mov %o2, %o0
+; V9-NEXT: fcmps %fcc0, %f0, %f1
+; V9-NEXT: movne %fcc0, %o1, %o0
+; V9-NEXT: retl
+; V9-NEXT: add %sp, 96, %sp
+;
+; SPARC64-LABEL: test_select_int_fcc:
+; SPARC64: ! %bb.0: ! %entry
+; SPARC64-NEXT: sethi %h44(.LCPI4_0), %o0
+; SPARC64-NEXT: add %o0, %m44(.LCPI4_0), %o0
+; SPARC64-NEXT: sllx %o0, 12, %o0
+; SPARC64-NEXT: ld [%o0+%l44(.LCPI4_0)], %f0
+; SPARC64-NEXT: mov %o2, %o0
+; SPARC64-NEXT: fcmps %fcc0, %f1, %f0
+; SPARC64-NEXT: retl
+; SPARC64-NEXT: movne %fcc0, %o1, %o0
entry:
-;V8-LABEL: test_select_int_fcc:
-;V8: fcmps
-;V8-NEXT: nop
-;V8: {{fbe|fbne}}
-;V9-LABEL: test_select_int_fcc:
-;V9: fcmps
-;V9-NOT: nop
-;V9-NOT: {{fbe|fbne}}
-;V9: mov{{e|ne}} %fcc0
%0 = fcmp une float %f, 0.000000e+00
%a.b = select i1 %0, i32 %a, i32 %b
ret i32 %a.b
}
-
-define float @test_select_fp_fcc(float %f, float %f1, float %f2) nounwind readnone noinline {
+define float @test_select_fp_fcc(float %f, float %f1, float %f2) nounwind {
+; V8-LABEL: test_select_fp_fcc:
+; V8: ! %bb.0: ! %entry
+; V8-NEXT: add %sp, -104, %sp
+; V8-NEXT: st %o0, [%sp+92]
+; V8-NEXT: st %o2, [%sp+100]
+; V8-NEXT: st %o1, [%sp+96]
+; V8-NEXT: ld [%sp+92], %f0
+; V8-NEXT: sethi %hi(.LCPI5_0), %o0
+; V8-NEXT: ld [%o0+%lo(.LCPI5_0)], %f1
+; V8-NEXT: fcmps %f0, %f1
+; V8-NEXT: nop
+; V8-NEXT: fbne .LBB5_2
+; V8-NEXT: nop
+; V8-NEXT: ! %bb.1: ! %entry
+; V8-NEXT: ld [%sp+100], %f0
+; V8-NEXT: retl
+; V8-NEXT: add %sp, 104, %sp
+; V8-NEXT: .LBB5_2:
+; V8-NEXT: ld [%sp+96], %f0
+; V8-NEXT: retl
+; V8-NEXT: add %sp, 104, %sp
+;
+; V9-LABEL: test_select_fp_fcc:
+; V9: ! %bb.0: ! %entry
+; V9-NEXT: add %sp, -104, %sp
+; V9-NEXT: st %o0, [%sp+92]
+; V9-NEXT: st %o2, [%sp+100]
+; V9-NEXT: st %o1, [%sp+96]
+; V9-NEXT: ld [%sp+92], %f1
+; V9-NEXT: ld [%sp+100], %f0
+; V9-NEXT: sethi %hi(.LCPI5_0), %o0
+; V9-NEXT: ld [%o0+%lo(.LCPI5_0)], %f2
+; V9-NEXT: ld [%sp+96], %f3
+; V9-NEXT: fcmps %fcc0, %f1, %f2
+; V9-NEXT: fmovsne %fcc0, %f3, %f0
+; V9-NEXT: retl
+; V9-NEXT: add %sp, 104, %sp
+;
+; SPARC64-LABEL: test_select_fp_fcc:
+; SPARC64: ! %bb.0: ! %entry
+; SPARC64-NEXT: sethi %h44(.LCPI5_0), %o0
+; SPARC64-NEXT: add %o0, %m44(.LCPI5_0), %o0
+; SPARC64-NEXT: sllx %o0, 12, %o0
+; SPARC64-NEXT: ld [%o0+%l44(.LCPI5_0)], %f2
+; SPARC64-NEXT: fmovs %f5, %f0
+; SPARC64-NEXT: fcmps %fcc0, %f1, %f2
+; SPARC64-NEXT: retl
+; SPARC64-NEXT: fmovsne %fcc0, %f3, %f0
entry:
-;V8-LABEL: test_select_fp_fcc:
-;V8: fcmps
-;V8: {{fbe|fbne}}
-;V9-LABEL: test_select_fp_fcc:
-;V9: fcmps
-;V9-NOT: {{fbe|fbne}}
-;V9: fmovs{{e|ne}} %fcc0
%0 = fcmp une float %f, 0.000000e+00
%1 = select i1 %0, float %f1, float %f2
ret float %1
}
-define double @test_select_dfp_fcc(double %f, double %f1, double %f2) nounwind readnone noinline {
+define double @test_select_dfp_fcc(double %f, double %f1, double %f2) nounwind {
+; V8-LABEL: test_select_dfp_fcc:
+; V8: ! %bb.0: ! %entry
+; V8-NEXT: add %sp, -120, %sp
+; V8-NEXT: ! kill: def $o1 killed $o1 killed $o0_o1 def $o0_o1
+; V8-NEXT: ! kill: def $o5 killed $o5 killed $o4_o5 def $o4_o5
+; V8-NEXT: ! kill: def $o3 killed $o3 killed $o2_o3 def $o2_o3
+; V8-NEXT: ! kill: def $o0 killed $o0 killed $o0_o1 def $o0_o1
+; V8-NEXT: std %o0, [%sp+112]
+; V8-NEXT: ! kill: def $o4 killed $o4 killed $o4_o5 def $o4_o5
+; V8-NEXT: std %o4, [%sp+96]
+; V8-NEXT: ! kill: def $o2 killed $o2 killed $o2_o3 def $o2_o3
+; V8-NEXT: std %o2, [%sp+104]
+; V8-NEXT: ldd [%sp+112], %f0
+; V8-NEXT: sethi %hi(.LCPI6_0), %o0
+; V8-NEXT: ldd [%o0+%lo(.LCPI6_0)], %f2
+; V8-NEXT: fcmpd %f0, %f2
+; V8-NEXT: nop
+; V8-NEXT: fbne .LBB6_2
+; V8-NEXT: nop
+; V8-NEXT: ! %bb.1: ! %entry
+; V8-NEXT: ldd [%sp+96], %f0
+; V8-NEXT: retl
+; V8-NEXT: add %sp, 120, %sp
+; V8-NEXT: .LBB6_2:
+; V8-NEXT: ldd [%sp+104], %f0
+; V8-NEXT: retl
+; V8-NEXT: add %sp, 120, %sp
+;
+; V9-LABEL: test_select_dfp_fcc:
+; V9: ! %bb.0: ! %entry
+; V9-NEXT: add %sp, -120, %sp
+; V9-NEXT: ! kill: def $o1 killed $o1 killed $o0_o1 def $o0_o1
+; V9-NEXT: ! kill: def $o5 killed $o5 killed $o4_o5 def $o4_o5
+; V9-NEXT: ! kill: def $o3 killed $o3 killed $o2_o3 def $o2_o3
+; V9-NEXT: ! kill: def $o0 killed $o0 killed $o0_o1 def $o0_o1
+; V9-NEXT: std %o0, [%sp+112]
+; V9-NEXT: ! kill: def $o4 killed $o4 killed $o4_o5 def $o4_o5
+; V9-NEXT: std %o4, [%sp+96]
+; V9-NEXT: ! kill: def $o2 killed $o2 killed $o2_o3 def $o2_o3
+; V9-NEXT: std %o2, [%sp+104]
+; V9-NEXT: ldd [%sp+112], %f2
+; V9-NEXT: ldd [%sp+96], %f0
+; V9-NEXT: sethi %hi(.LCPI6_0), %o0
+; V9-NEXT: ldd [%o0+%lo(.LCPI6_0)], %f4
+; V9-NEXT: ldd [%sp+104], %f6
+; V9-NEXT: fcmpd %fcc0, %f2, %f4
+; V9-NEXT: fmovdne %fcc0, %f6, %f0
+; V9-NEXT: retl
+; V9-NEXT: add %sp, 120, %sp
+;
+; SPARC64-LABEL: test_select_dfp_fcc:
+; SPARC64: ! %bb.0: ! %entry
+; SPARC64-NEXT: sethi %h44(.LCPI6_0), %o0
+; SPARC64-NEXT: add %o0, %m44(.LCPI6_0), %o0
+; SPARC64-NEXT: sllx %o0, 12, %o0
+; SPARC64-NEXT: ldd [%o0+%l44(.LCPI6_0)], %f6
+; SPARC64-NEXT: fcmpd %fcc0, %f0, %f6
+; SPARC64-NEXT: fmovdne %fcc0, %f2, %f4
+; SPARC64-NEXT: fmovd %f4, %f0
+; SPARC64-NEXT: retl
+; SPARC64-NEXT: nop
entry:
-;V8-LABEL: test_select_dfp_fcc:
-;V8: fcmpd
-;V8-NEXT: nop
-;V8: {{fbne|fbe}}
-;V9-LABEL: test_select_dfp_fcc:
-;V9: fcmpd
-;V9-NOT: nop
-;V9-NOT: {{fbne|fbe}}
-;V9: fmovd{{e|ne}} %fcc0
%0 = fcmp une double %f, 0.000000e+00
%1 = select i1 %0, double %f1, double %f2
ret double %1
}
-define i32 @test_float_cc(double %a, double %b, i32 %c, i32 %d) {
+define i32 @test_float_cc(double %a, double %b, i32 %c, i32 %d) nounwind {
+; V8-LABEL: test_float_cc:
+; V8: ! %bb.0: ! %entry
+; V8-NEXT: add %sp, -112, %sp
+; V8-NEXT: ! kill: def $o3 killed $o3 killed $o2_o3 def $o2_o3
+; V8-NEXT: ! kill: def $o1 killed $o1 killed $o0_o1 def $o0_o1
+; V8-NEXT: ! kill: def $o2 killed $o2 killed $o2_o3 def $o2_o3
+; V8-NEXT: std %o2, [%sp+96]
+; V8-NEXT: ! kill: def $o0 killed $o0 killed $o0_o1 def $o0_o1
+; V8-NEXT: std %o0, [%sp+104]
+; V8-NEXT: ldd [%sp+104], %f2
+; V8-NEXT: sethi %hi(.LCPI7_0), %o0
+; V8-NEXT: ldd [%o0+%lo(.LCPI7_0)], %f0
+; V8-NEXT: fcmpd %f2, %f0
+; V8-NEXT: nop
+; V8-NEXT: fbuge .LBB7_3
+; V8-NEXT: nop
+; V8-NEXT: ! %bb.1: ! %loop.2
+; V8-NEXT: ldd [%sp+96], %f2
+; V8-NEXT: fcmpd %f2, %f0
+; V8-NEXT: nop
+; V8-NEXT: fbule .LBB7_3
+; V8-NEXT: nop
+; V8-NEXT: ! %bb.2: ! %exit.1
+; V8-NEXT: mov 1, %o0
+; V8-NEXT: retl
+; V8-NEXT: add %sp, 112, %sp
+; V8-NEXT: .LBB7_3: ! %loop
+; V8-NEXT: ! =>This Inner Loop Header: Depth=1
+; V8-NEXT: cmp %o4, 10
+; V8-NEXT: be .LBB7_3
+; V8-NEXT: nop
+; V8-NEXT: ! %bb.4: ! %exit.0
+; V8-NEXT: mov %g0, %o0
+; V8-NEXT: retl
+; V8-NEXT: add %sp, 112, %sp
+;
+; V9-LABEL: test_float_cc:
+; V9: ! %bb.0: ! %entry
+; V9-NEXT: add %sp, -112, %sp
+; V9-NEXT: ! kill: def $o3 killed $o3 killed $o2_o3 def $o2_o3
+; V9-NEXT: ! kill: def $o1 killed $o1 killed $o0_o1 def $o0_o1
+; V9-NEXT: ! kill: def $o2 killed $o2 killed $o2_o3 def $o2_o3
+; V9-NEXT: std %o2, [%sp+96]
+; V9-NEXT: ! kill: def $o0 killed $o0 killed $o0_o1 def $o0_o1
+; V9-NEXT: std %o0, [%sp+104]
+; V9-NEXT: ldd [%sp+104], %f2
+; V9-NEXT: sethi %hi(.LCPI7_0), %o0
+; V9-NEXT: ldd [%o0+%lo(.LCPI7_0)], %f0
+; V9-NEXT: fcmpd %fcc0, %f2, %f0
+; V9-NEXT: fbuge %fcc0, .LBB7_3
+; V9-NEXT: nop
+; V9-NEXT: ! %bb.1: ! %loop.2
+; V9-NEXT: ldd [%sp+96], %f2
+; V9-NEXT: fcmpd %fcc0, %f2, %f0
+; V9-NEXT: fbule %fcc0, .LBB7_3
+; V9-NEXT: nop
+; V9-NEXT: ! %bb.2: ! %exit.1
+; V9-NEXT: mov 1, %o0
+; V9-NEXT: retl
+; V9-NEXT: add %sp, 112, %sp
+; V9-NEXT: .LBB7_3: ! %loop
+; V9-NEXT: ! =>This Inner Loop Header: Depth=1
+; V9-NEXT: cmp %o4, 10
+; V9-NEXT: be %icc, .LBB7_3
+; V9-NEXT: nop
+; V9-NEXT: ! %bb.4: ! %exit.0
+; V9-NEXT: mov %g0, %o0
+; V9-NEXT: retl
+; V9-NEXT: add %sp, 112, %sp
+;
+; SPARC64-LABEL: test_float_cc:
+; SPARC64: ! %bb.0: ! %entry
+; SPARC64-NEXT: sethi %h44(.LCPI7_0), %o0
+; SPARC64-NEXT: add %o0, %m44(.LCPI7_0), %o0
+; SPARC64-NEXT: sllx %o0, 12, %o0
+; SPARC64-NEXT: ldd [%o0+%l44(.LCPI7_0)], %f4
+; SPARC64-NEXT: fcmpd %fcc0, %f0, %f4
+; SPARC64-NEXT: fbuge %fcc0, .LBB7_3
+; SPARC64-NEXT: nop
+; SPARC64-NEXT: ! %bb.1: ! %loop.2
+; SPARC64-NEXT: fcmpd %fcc0, %f2, %f4
+; SPARC64-NEXT: fbule %fcc0, .LBB7_3
+; SPARC64-NEXT: nop
+; SPARC64-NEXT: ! %bb.2: ! %exit.1
+; SPARC64-NEXT: retl
+; SPA...
[truncated]
|
You can test this locally with the following command:git-clang-format --diff fe07d9aa410518c5b631a065ddc5782a623af030 60d3467f2287dfb15358aa867647d4052063224f --extensions cpp -- llvm/lib/Target/Sparc/SparcISelLowering.cppView the diff from clang-format here.diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index 41aa2dcffe..6ba74651d5 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -3229,7 +3229,8 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::FABS:
case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9);
case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this);
- case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this);
+ case ISD::FP_ROUND:
+ return LowerF128_FPROUND(Op, DAG, *this);
case ISD::UMULO:
case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this);
case ISD::ATOMIC_LOAD:
|
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/125/builds/991 Here is the relevant piece of the build log for the reference: |
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The default lowering produces fewer instructions.