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[RISCV] Rename hasVInstructionsBF16 to hasVInstructionsBF16Minimal. NFC #101080

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Merged
merged 1 commit into from
Jul 30, 2024
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[RISCV] Rename hasVInstructionsBF16 to hasVInstructionsBF16Minimal. NFC #101080

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2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -329,7 +329,7 @@ static bool isLegalElementTypeForRVV(Type *EltTy,
if (EltTy->isHalfTy())
return Subtarget.hasVInstructionsF16();
if (EltTy->isBFloatTy())
return Subtarget.hasVInstructionsBF16();
return Subtarget.hasVInstructionsBF16Minimal();
if (EltTy->isFloatTy())
return Subtarget.hasVInstructionsF32();
if (EltTy->isDoubleTy())
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2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVFeatures.td
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Expand Up @@ -870,7 +870,7 @@ def HasVInstructionsF16Minimal : Predicate<"Subtarget->hasVInstructionsF16Minima
"'Zvfhmin' (Vector Half-Precision Floating-Point Minimal) or "
"'Zvfh' (Vector Half-Precision Floating-Point)">;

def HasVInstructionsBF16 : Predicate<"Subtarget->hasVInstructionsBF16()">;
def HasVInstructionsBF16Minimal : Predicate<"Subtarget->hasVInstructionsBF16Minimal()">;
def HasVInstructionsF16 : Predicate<"Subtarget->hasVInstructionsF16()">;
def HasVInstructionsF64 : Predicate<"Subtarget->hasVInstructionsF64()">;

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9 changes: 5 additions & 4 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Expand Up @@ -198,7 +198,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
for (MVT VT : F16VecVTs)
addRegClassForRVV(VT);

if (Subtarget.hasVInstructionsBF16())
if (Subtarget.hasVInstructionsBF16Minimal())
for (MVT VT : BF16VecVTs)
addRegClassForRVV(VT);

Expand Down Expand Up @@ -1092,7 +1092,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
}

// TODO: Could we merge some code with zvfhmin?
if (Subtarget.hasVInstructionsBF16()) {
if (Subtarget.hasVInstructionsBF16Minimal()) {
for (MVT VT : BF16VecVTs) {
if (!isTypeLegal(VT))
continue;
Expand Down Expand Up @@ -2637,7 +2637,7 @@ static bool useRVVForFixedLengthVectorVT(MVT VT,
return false;
break;
case MVT::bf16:
if (!Subtarget.hasVInstructionsBF16())
if (!Subtarget.hasVInstructionsBF16Minimal())
return false;
break;
case MVT::f32:
Expand Down Expand Up @@ -6834,7 +6834,8 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
Subtarget.hasStdExtZfhminOrZhinxmin() &&
!Subtarget.hasVInstructionsF16())) ||
(Op.getValueType().getScalarType() == MVT::bf16 &&
(Subtarget.hasVInstructionsBF16() && Subtarget.hasStdExtZfbfmin()))) {
(Subtarget.hasVInstructionsBF16Minimal() &&
Subtarget.hasStdExtZfbfmin()))) {
if (Op.getValueType() == MVT::nxv32f16 ||
Op.getValueType() == MVT::nxv32bf16)
return SplitVectorOp(Op, DAG);
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2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
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Expand Up @@ -751,7 +751,7 @@ class VPseudo<Instruction instr, LMULInfo m, dag outs, dag ins, int sew = 0> :

class GetVTypePredicates<VTypeInfo vti> {
list<Predicate> Predicates = !cond(!eq(vti.Scalar, f16) : [HasVInstructionsF16],
!eq(vti.Scalar, bf16) : [HasVInstructionsBF16],
!eq(vti.Scalar, bf16) : [HasVInstructionsBF16Minimal],
!eq(vti.Scalar, f32) : [HasVInstructionsAnyF],
!eq(vti.Scalar, f64) : [HasVInstructionsF64],
!eq(vti.SEW, 64) : [HasVInstructionsI64],
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2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
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Expand Up @@ -1430,7 +1430,7 @@ foreach fvtiToFWti = AllWidenableFloatVectors in {
foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
defvar fwti = fvtiToFWti.Wti;
let Predicates = [HasVInstructionsBF16] in
let Predicates = [HasVInstructionsBF16Minimal] in
def : Pat<(fvti.Vector (fpround (fwti.Vector fwti.RegClass:$rs1))),
(!cast<Instruction>("PseudoVFNCVTBF16_F_F_W_"#fvti.LMul.MX#"_E"#fvti.SEW)
(fvti.Vector (IMPLICIT_DEF)),
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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
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Expand Up @@ -2673,7 +2673,7 @@ foreach fvtiToFWti = AllWidenableFloatVectors in {
foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
defvar fwti = fvtiToFWti.Wti;
let Predicates = [HasVInstructionsBF16] in
let Predicates = [HasVInstructionsBF16Minimal] in
def : Pat<(fwti.Vector (any_riscv_fpextend_vl
(fvti.Vector fvti.RegClass:$rs1),
(fvti.Mask V0),
Expand Down Expand Up @@ -2731,7 +2731,7 @@ foreach fvtiToFWti = AllWidenableFloatVectors in {
foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
defvar fwti = fvtiToFWti.Wti;
let Predicates = [HasVInstructionsBF16] in
let Predicates = [HasVInstructionsBF16Minimal] in
def : Pat<(fvti.Vector (any_riscv_fpround_vl
(fwti.Vector fwti.RegClass:$rs1),
(fwti.Mask V0), VLOpFrag)),
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVSubtarget.h
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Expand Up @@ -225,7 +225,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool hasVInstructionsI64() const { return HasStdExtZve64x; }
bool hasVInstructionsF16Minimal() const { return HasStdExtZvfhmin; }
bool hasVInstructionsF16() const { return HasStdExtZvfh; }
bool hasVInstructionsBF16() const { return HasStdExtZvfbfmin; }
bool hasVInstructionsBF16Minimal() const { return HasStdExtZvfbfmin; }
bool hasVInstructionsF32() const { return HasStdExtZve32f; }
bool hasVInstructionsF64() const { return HasStdExtZve64d; }
// F16 and F64 both require F32.
Expand Down
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