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[AArch64] Fix MatchDup Lane Out Of Range In AArch64 #101275

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Merged
merged 1 commit into from
Aug 7, 2024
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[AArch64] Fix MatchDup Lane Out Of Range In AArch64 #101275

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10 changes: 8 additions & 2 deletions llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -288,10 +288,16 @@ bool matchDupFromBuildVector(int Lane, MachineInstr &MI,
MachineRegisterInfo &MRI,
ShuffleVectorPseudo &MatchInfo) {
assert(Lane >= 0 && "Expected positive lane?");
int NumElements = MRI.getType(MI.getOperand(1).getReg()).getNumElements();
// Test if the LHS is a BUILD_VECTOR. If it is, then we can just reference the
// lane's definition directly.
auto *BuildVecMI = getOpcodeDef(TargetOpcode::G_BUILD_VECTOR,
MI.getOperand(1).getReg(), MRI);
auto *BuildVecMI =
getOpcodeDef(TargetOpcode::G_BUILD_VECTOR,
MI.getOperand(Lane < NumElements ? 1 : 2).getReg(), MRI);
// If Lane >= NumElements then it is point to RHS, just check from RHS
if (NumElements <= Lane)
Lane -= NumElements;

if (!BuildVecMI)
return false;
Register Reg = BuildVecMI->getOperand(Lane + 1).getReg();
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29 changes: 29 additions & 0 deletions llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir
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Expand Up @@ -367,3 +367,32 @@ body: |
%shuf:_(<4 x s32>) = G_SHUFFLE_VECTOR %buildvec(<4 x s32>), %undef, shufflemask(0, 0, 0, 0)
$q0 = COPY %shuf(<4 x s32>)
RET_ReallyLR implicit $q0

...
---
name: build_vector_rhs
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $w0, $w1, $w2, $w3, $w4
; The G_SHUFFLE_VECTOR is fed by a G_BUILD_VECTOR, and the 0th input
; operand is not a constant. We should get a G_DUP.
;
; CHECK-LABEL: name: build_vector
; CHECK: liveins: $w0, $w1, $w2, $w3, $w4
; CHECK: %lane_1:_(s32) = COPY $w1
; CHECK: %shuf:_(<4 x s32>) = G_DUP %lane_1(s32)
; CHECK: $q0 = COPY %shuf(<4 x s32>)
; CHECK: RET_ReallyLR implicit $q0
%lane_0:_(s32) = COPY $w0
%lane_1:_(s32) = COPY $w1
%b:_(s32) = COPY $w2
%c:_(s32) = COPY $w3
%d:_(s32) = COPY $w4
%buildvec0:_(<4 x s32>) = G_BUILD_VECTOR %lane_0(s32), %b(s32), %c(s32), %d(s32)
%buildvec1:_(<4 x s32>) = G_BUILD_VECTOR %lane_1(s32), %b(s32), %c(s32), %d(s32)
%shuf:_(<4 x s32>) = G_SHUFFLE_VECTOR %buildvec0(<4 x s32>), %buildvec1, shufflemask(4, 4, 4, 4)
$q0 = COPY %shuf(<4 x s32>)
RET_ReallyLR implicit $q0
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