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[AArch64] Split FeatureLS64 to LS64_ACCDATA and LS64_V. #101712

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[AArch64] Split FeatureLS64 to LS64_ACCDATA and LS64_V. #101712

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2fe8ef6
[AArch64] Split FeatureLS64 to LS64_ACCDATA and LS64_V.
labrinea Aug 2, 2024
739bc85
Merge branch 'main' into split-ls64-features
labrinea Aug 27, 2024
15efdaa
Merge branch 'main' into split-ls64-features
labrinea Aug 30, 2024
0689b83
Merge branch 'main' into split-ls64-features
labrinea Sep 18, 2024
ab602c0
Merge branch 'main' into split-ls64-features
labrinea Sep 18, 2024
164041a
Changes from last revision:
labrinea Sep 18, 2024
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2 changes: 1 addition & 1 deletion clang/lib/Basic/Targets/AArch64.cpp
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Expand Up @@ -1071,7 +1071,7 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
HasBFloat16 = true;
if (Feature == "+lse")
HasLSE = true;
if (Feature == "+ls64")
if (Feature == "+ls64_accdata")
HasLS64 = true;
if (Feature == "+rand")
HasRandGen = true;
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8 changes: 5 additions & 3 deletions clang/test/CodeGen/aarch64-fmv-dependencies.c
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Expand Up @@ -66,13 +66,13 @@ __attribute__((target_version("i8mm"))) int fmv(void) { return 0; }
// CHECK: define dso_local i32 @fmv._Mjscvt() #[[jscvt:[0-9]+]] {
__attribute__((target_version("jscvt"))) int fmv(void) { return 0; }

// CHECK: define dso_local i32 @fmv._Mls64() #[[ATTR0:[0-9]+]] {
// CHECK: define dso_local i32 @fmv._Mls64() #[[ls64:[0-9]+]] {
__attribute__((target_version("ls64"))) int fmv(void) { return 0; }

// CHECK: define dso_local i32 @fmv._Mls64_accdata() #[[ls64_accdata:[0-9]+]] {
__attribute__((target_version("ls64_accdata"))) int fmv(void) { return 0; }

// CHECK: define dso_local i32 @fmv._Mls64_v() #[[ATTR0:[0-9]+]] {
// CHECK: define dso_local i32 @fmv._Mls64_v() #[[ls64_v:[0-9]+]] {
__attribute__((target_version("ls64_v"))) int fmv(void) { return 0; }

// CHECK: define dso_local i32 @fmv._Mlse() #[[lse:[0-9]+]] {
Expand Down Expand Up @@ -210,7 +210,9 @@ int caller() {
// CHECK: attributes #[[frintts]] = { {{.*}} "target-features"="+fp-armv8,+fptoint,+neon,+outline-atomics,+v8a"
// CHECK: attributes #[[i8mm]] = { {{.*}} "target-features"="+fp-armv8,+i8mm,+neon,+outline-atomics,+v8a"
// CHECK: attributes #[[jscvt]] = { {{.*}} "target-features"="+fp-armv8,+jsconv,+neon,+outline-atomics,+v8a"
// CHECK: attributes #[[ls64_accdata]] = { {{.*}} "target-features"="+fp-armv8,+ls64,+neon,+outline-atomics,+v8a"
// CHECK: attributes #[[ls64]] = { {{.*}} "target-features"="+fp-armv8,+ls64,+neon,+outline-atomics,+v8a"
// CHECK: attributes #[[ls64_accdata]] = { {{.*}} "target-features"="+fp-armv8,+ls64,+ls64_accdata,+ls64_v,+neon,+outline-atomics,+v8a"
// CHECK: attributes #[[ls64_v]] = { {{.*}} "target-features"="+fp-armv8,+ls64,+ls64_v,+neon,+outline-atomics,+v8a"
// CHECK: attributes #[[lse]] = { {{.*}} "target-features"="+fp-armv8,+lse,+neon,+outline-atomics,+v8a"
// CHECK: attributes #[[memtag2]] = { {{.*}} "target-features"="+fp-armv8,+mte,+neon,+outline-atomics,+v8a"
// CHECK: attributes #[[mops]] = { {{.*}} "target-features"="+fp-armv8,+mops,+neon,+outline-atomics,+v8a"
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2 changes: 1 addition & 1 deletion clang/test/CodeGen/aarch64-ls64-inline-asm.c
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@@ -1,5 +1,5 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple aarch64 -target-feature +ls64 -O1 -emit-llvm -x c %s -o - | FileCheck %s
// RUN: %clang_cc1 -triple aarch64 -target-feature +ls64_accdata -O1 -emit-llvm -x c %s -o - | FileCheck %s

struct foo { unsigned long long x[8]; };

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8 changes: 4 additions & 4 deletions clang/test/CodeGen/aarch64-ls64.c
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@@ -1,8 +1,8 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple aarch64 -target-feature +ls64 -emit-llvm -x c %s -o - | FileCheck --check-prefixes=CHECK-C %s
// RUN: %clang_cc1 -triple aarch64 -target-feature +ls64 -emit-llvm -x c++ %s -o - | FileCheck --check-prefixes=CHECK-CXX %s
// RUN: %clang_cc1 -triple aarch64_be-eabi -target-feature +ls64 -emit-llvm -x c %s -o - | FileCheck --check-prefixes=CHECK-C %s
// RUN: %clang_cc1 -triple aarch64_be-eabi -target-feature +ls64 -emit-llvm -x c++ %s -o - | FileCheck --check-prefixes=CHECK-CXX %s
// RUN: %clang_cc1 -triple aarch64 -target-feature +ls64 -target-feature +ls64_v -target-feature +ls64_accdata -emit-llvm -x c %s -o - | FileCheck --check-prefixes=CHECK-C %s
// RUN: %clang_cc1 -triple aarch64 -target-feature +ls64 -target-feature +ls64_v -target-feature +ls64_accdata -emit-llvm -x c++ %s -o - | FileCheck --check-prefixes=CHECK-CXX %s
// RUN: %clang_cc1 -triple aarch64_be-eabi -target-feature +ls64 -target-feature +ls64_v -target-feature +ls64_accdata -emit-llvm -x c %s -o - | FileCheck --check-prefixes=CHECK-C %s
// RUN: %clang_cc1 -triple aarch64_be-eabi -target-feature +ls64 -target-feature +ls64_v -target-feature +ls64_accdata -emit-llvm -x c++ %s -o - | FileCheck --check-prefixes=CHECK-CXX %s

#include <arm_acle.h>

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112 changes: 57 additions & 55 deletions clang/test/CodeGen/attr-target-version.c
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4 changes: 2 additions & 2 deletions clang/test/CodeGenCXX/attr-target-clones-aarch64.cpp
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Expand Up @@ -240,8 +240,8 @@ void run_foo_tml() {
// CHECK-NEXT: ret ptr @_ZN7MyClassIisE7foo_tmlEv.default
//
//.
// CHECK: attributes #[[ATTR0]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon" }
// CHECK: attributes #[[ATTR1]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ls64" }
// CHECK: attributes #[[ATTR0]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+ls64,+ls64_v,+neon" }
// CHECK: attributes #[[ATTR1]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ls64,+ls64_accdata,+ls64_v" }
// CHECK: attributes #[[ATTR2]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
// CHECK: attributes #[[ATTR3]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fptoint" }
// CHECK: attributes #[[ATTR4]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sme,+sme-f64f64" }
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8 changes: 8 additions & 0 deletions clang/test/Driver/aarch64-ls64.c
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Expand Up @@ -2,6 +2,8 @@

// RUN: %clang -### --target=aarch64-none-elf -march=armv8.7-a+ls64 %s 2>&1 | FileCheck %s
// CHECK: "-target-feature" "+ls64"
// CHECK: "-target-feature" "+ls64_accdata"
// CHECK: "-target-feature" "+ls64_v"

// RUN: %clang -### --target=aarch64-none-elf -march=armv8.7-a+nols64 %s 2>&1 | FileCheck %s --check-prefix=ABSENT_LS64

Expand All @@ -11,3 +13,9 @@
// RUN: %clang -### --target=aarch64-none-elf -march=armv8.7-a %s 2>&1 | FileCheck %s --check-prefix=ABSENT_LS64
// ABSENT_LS64-NOT: "-target-feature" "+ls64"
// ABSENT_LS64-NOT: "-target-feature" "-ls64"

// Test that nols64 disables all three FEAT_LS64, FEAT_LS64_V and FEAT_LS64_ACCDATA.
// RUN: %clang -### --target=aarch64-none-elf -march=armv8.7-a+ls64+nols64 %s 2>&1 | FileCheck %s --check-prefix=NOLS64
// NOLS64: "-target-feature" "-ls64"
// NOLS64: "-target-feature" "-ls64_accdata"
// NOLS64: "-target-feature" "-ls64_v"
4 changes: 3 additions & 1 deletion clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v3.c
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Expand Up @@ -33,7 +33,9 @@
// CHECK-NEXT: FEAT_LOR Enable Armv8.1-A Limited Ordering Regions extension
// CHECK-NEXT: FEAT_LRCPC Enable support for RCPC extension
// CHECK-NEXT: FEAT_LRCPC2 Enable Armv8.4-A RCPC instructions with Immediate Offsets
// CHECK-NEXT: FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA Enable Armv8.7-A LD64B/ST64B Accelerator Extension
// CHECK-NEXT: FEAT_LS64 Enable single-copy atomic 64-byte loads and stores without status result
// CHECK-NEXT: FEAT_LS64_ACCDATA Enable single-copy atomic 64-byte EL0 stores with status result
// CHECK-NEXT: FEAT_LS64_V Enable single-copy atomic 64-byte stores with status result
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
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4 changes: 3 additions & 1 deletion clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v3ae.c
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Expand Up @@ -33,7 +33,9 @@
// CHECK-NEXT: FEAT_LOR Enable Armv8.1-A Limited Ordering Regions extension
// CHECK-NEXT: FEAT_LRCPC Enable support for RCPC extension
// CHECK-NEXT: FEAT_LRCPC2 Enable Armv8.4-A RCPC instructions with Immediate Offsets
// CHECK-NEXT: FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA Enable Armv8.7-A LD64B/ST64B Accelerator Extension
// CHECK-NEXT: FEAT_LS64 Enable single-copy atomic 64-byte loads and stores without status result
// CHECK-NEXT: FEAT_LS64_ACCDATA Enable single-copy atomic 64-byte EL0 stores with status result
// CHECK-NEXT: FEAT_LS64_V Enable single-copy atomic 64-byte stores with status result
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
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2 changes: 1 addition & 1 deletion clang/test/Driver/print-supported-extensions-aarch64.c
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Expand Up @@ -32,7 +32,7 @@
// CHECK-NEXT: i8mm FEAT_I8MM Enable Matrix Multiply Int8 Extension
// CHECK-NEXT: ite FEAT_ITE Enable Armv9.4-A Instrumentation Extension
// CHECK-NEXT: jscvt FEAT_JSCVT Enable Armv8.3-A JavaScript FP conversion instructions
// CHECK-NEXT: ls64 FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA Enable Armv8.7-A LD64B/ST64B Accelerator Extension
// CHECK-NEXT: ls64 FEAT_LS64_ACCDATA Enable single-copy atomic 64-byte EL0 stores with status result
// CHECK-NEXT: lse FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: lse128 FEAT_LSE128 Enable Armv9.4-A 128-bit Atomic instructions
// CHECK-NEXT: lut FEAT_LUT Enable Lookup Table instructions
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4 changes: 2 additions & 2 deletions clang/test/Sema/attr-target-clones-aarch64.c
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Expand Up @@ -5,7 +5,7 @@ void __attribute__((target_clones("fp16+sve2-aes", "sb+sve2-sha3+rcpc3+mops", "r
// expected-warning@+1 {{unsupported 'default' in the 'target_clones' attribute string; 'target_clones' attribute ignored}}
void __attribute__((target_clones("default+sha3"))) warn1(void);
// expected-warning@+1 {{version list contains entries that don't impact code generation}}
void __attribute__((target_clones("ssbs+ls64"))) warn2(void);
void __attribute__((target_clones("ssbs"))) warn2(void);

// expected-error@+2 {{'target_clones' and 'target_version' attributes are not compatible}}
// expected-note@+1 {{conflicting attribute is here}}
Expand All @@ -24,7 +24,7 @@ int __attribute__((target_clones("rng", "fp16fml+fp", "default"))) redecl4(void)
// expected-error@+3 {{'target_clones' attribute does not match previous declaration}}
// expected-note@-2 {{previous declaration is here}}
// expected-warning@+1 {{version list contains entries that don't impact code generation}}
int __attribute__((target_clones("dgh+memtag+rpres+ls64_v", "ebf16+dpb+sha1", "default"))) redecl4(void) { return 1; }
int __attribute__((target_clones("dgh+memtag+rpres", "ebf16+dpb+sha1", "default"))) redecl4(void) { return 1; }

int __attribute__((target_version("flagm2"))) redef2(void) { return 1; }
// expected-error@+2 {{multiversioned function redeclarations require identical target attributes}}
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6 changes: 3 additions & 3 deletions llvm/lib/Target/AArch64/AArch64FMV.td
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Expand Up @@ -58,9 +58,9 @@ def : FMVExtension<"fp16fml", "FEAT_FP16FML", "+fp16fml,+fullfp16,+fp-armv8,+neo
def : FMVExtension<"frintts", "FEAT_FRINTTS", "+fptoint", 250>;
def : FMVExtension<"i8mm", "FEAT_I8MM", "+i8mm", 270>;
def : FMVExtension<"jscvt", "FEAT_JSCVT", "+fp-armv8,+neon,+jsconv", 210>;
def : FMVExtension<"ls64", "FEAT_LS64", "", 520>;
def : FMVExtension<"ls64_accdata", "FEAT_LS64_ACCDATA", "+ls64", 540>;
def : FMVExtension<"ls64_v", "FEAT_LS64_V", "", 530>;
def : FMVExtension<"ls64", "FEAT_LS64", "+ls64", 520>;
def : FMVExtension<"ls64_accdata", "FEAT_LS64_ACCDATA", "+ls64,+ls64_v,+ls64_accdata", 540>;
def : FMVExtension<"ls64_v", "FEAT_LS64_V", "+ls64,+ls64_v", 530>;
def : FMVExtension<"lse", "FEAT_LSE", "+lse", 80>;
def : FMVExtension<"memtag", "FEAT_MEMTAG", "", 440>;
def : FMVExtension<"memtag2", "FEAT_MEMTAG2", "+mte", 450>;
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14 changes: 11 additions & 3 deletions llvm/lib/Target/AArch64/AArch64Features.td
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Expand Up @@ -305,9 +305,17 @@ def FeatureWFxT : ExtensionWithMArch<"wfxt", "WFxT", "FEAT_WFxT",
def FeatureHCX : Extension<"hcx", "HCX", "FEAT_HCX",
"Enable Armv8.7-A HCRX_EL2 system register">;

def FeatureLS64 : ExtensionWithMArch<"ls64", "LS64",
"FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA",
"Enable Armv8.7-A LD64B/ST64B Accelerator Extension">;
def FeatureLS64 : Extension<"ls64", "LS64", "FEAT_LS64",
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The internal feature name +ls64 would need to be something like +ls64only to preserve backwards compatibility of the IR.

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I do think this will create confusion. I would prefer something like "ls64_no_status_result", which is also ugly but more informative. I think it is not worth maintaining backwards compatibility at the expense of code maintainability in cases like this. I consider the IR metadata to be more volatile than the command line or anything user facing like the .archextension in assembler.

"Enable single-copy atomic 64-byte loads and stores without status result">;

def FeatureLS64_V : Extension<"ls64_v", "LS64_V", "FEAT_LS64_V",
"Enable single-copy atomic 64-byte stores with status result",
[FeatureLS64]>;

let UserVisibleName = "ls64" in
def FeatureLS64_ACCDATA : ExtensionWithMArch<"ls64_accdata", "LS64_ACCDATA", "FEAT_LS64_ACCDATA",
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Internal feature name ls64_accdata could be changed to ls64 to keep backwards compatibility of IR... however this would potentially make things even more confusing, and we are allowed to drop non-debug metadata.

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Same here. The name ls64 is less informative and having it alongside ls64only (or whichever name we decide) is just confusing than anything else in my opinion.

"Enable single-copy atomic 64-byte EL0 stores with status result",
[FeatureLS64_V]>;

def FeatureSPE_EEF : Extension<"spe-eef", "SPE_EEF", "FEAT_SPEv1p2",
"Enable extra register in the Statistical Profiling Extension">;
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23 changes: 16 additions & 7 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.td
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Expand Up @@ -286,6 +286,10 @@ def HasWFxT : Predicate<"Subtarget->hasWFxT()">,
AssemblerPredicateWithAll<(all_of FeatureWFxT), "wfxt">;
def HasLS64 : Predicate<"Subtarget->hasLS64()">,
AssemblerPredicateWithAll<(all_of FeatureLS64), "ls64">;
def HasLS64_V : Predicate<"Subtarget->hasLS64_V()">,
AssemblerPredicateWithAll<(all_of FeatureLS64_V), "ls64_v">;
def HasLS64_ACCDATA : Predicate<"Subtarget->hasLS64_ACCDATA()">,
AssemblerPredicateWithAll<(all_of FeatureLS64_ACCDATA), "ls64_accdata">;
def HasBRBE : Predicate<"Subtarget->hasBRBE()">,
AssemblerPredicateWithAll<(all_of FeatureBRBE), "brbe">;
def HasSPE_EEF : Predicate<"Subtarget->hasSPE_EEF()">,
Expand Down Expand Up @@ -9872,20 +9876,25 @@ foreach i = 0-7 in {
(EXTRACT_SUBREG $val, !cast<SubRegIndex>("x8sub_"#i))>;
}

class ST64BPattern<Intrinsic intrinsic, Instruction instruction>
: Pat<(intrinsic GPR64sp:$addr, GPR64:$x0, GPR64:$x1, GPR64:$x2, GPR64:$x3, GPR64:$x4, GPR64:$x5, GPR64:$x6, GPR64:$x7),
(instruction (REG_SEQUENCE GPR64x8Class, $x0, x8sub_0, $x1, x8sub_1, $x2, x8sub_2, $x3, x8sub_3, $x4, x8sub_4, $x5, x8sub_5, $x6, x8sub_6, $x7, x8sub_7), $addr)>;

let Predicates = [HasLS64] in {
def LD64B: LoadStore64B<0b101, "ld64b", (ins GPR64sp:$Rn),
(outs GPR64x8:$Rt)>;
def ST64B: LoadStore64B<0b001, "st64b", (ins GPR64x8:$Rt, GPR64sp:$Rn),
(outs)>;
def ST64BV: Store64BV<0b011, "st64bv">;
def ST64BV0: Store64BV<0b010, "st64bv0">;

class ST64BPattern<Intrinsic intrinsic, Instruction instruction>
: Pat<(intrinsic GPR64sp:$addr, GPR64:$x0, GPR64:$x1, GPR64:$x2, GPR64:$x3, GPR64:$x4, GPR64:$x5, GPR64:$x6, GPR64:$x7),
(instruction (REG_SEQUENCE GPR64x8Class, $x0, x8sub_0, $x1, x8sub_1, $x2, x8sub_2, $x3, x8sub_3, $x4, x8sub_4, $x5, x8sub_5, $x6, x8sub_6, $x7, x8sub_7), $addr)>;

def : ST64BPattern<int_aarch64_st64b, ST64B>;
}

let Predicates = [HasLS64_V] in {
def ST64BV: Store64BV<0b011, "st64bv">;
def : ST64BPattern<int_aarch64_st64bv, ST64BV>;
}

let Predicates = [HasLS64_ACCDATA] in {
def ST64BV0: Store64BV<0b010, "st64bv0">;
def : ST64BPattern<int_aarch64_st64bv0, ST64BV0>;
}

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4 changes: 2 additions & 2 deletions llvm/lib/Target/AArch64/AArch64Processors.td
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Expand Up @@ -971,7 +971,7 @@ def ProcessorFeatures {
FeatureComplxNum, FeatureCRC, FeatureFPARMv8, FeatureJS, FeatureLSE,
FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM];
list<SubtargetFeature> NeoverseV3 = [HasV9_2aOps, FeatureETE, FeatureFP16FML,
FeatureFullFP16, FeatureLS64, FeatureMTE,
FeatureFullFP16, FeatureLS64_ACCDATA, FeatureMTE,
FeaturePerfMon, FeatureRandGen, FeatureSPE,
FeatureCCIDX,
FeatureSPE_EEF, FeatureSVE2BitPerm, FeatureBRBE,
Expand All @@ -980,7 +980,7 @@ def ProcessorFeatures {
FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8, FeatureJS, FeatureLSE,
FeatureNEON, FeatureRAS, FeatureRCPC, FeatureRDM, FeatureRME];
list<SubtargetFeature> NeoverseV3AE = [HasV9_2aOps, FeatureETE, FeatureFP16FML,
FeatureFullFP16, FeatureLS64, FeatureMTE,
FeatureFullFP16, FeatureLS64_ACCDATA, FeatureMTE,
FeaturePerfMon, FeatureRandGen, FeatureSPE,
FeatureSPE_EEF, FeatureSVE2BitPerm, FeatureBRBE,
FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM,
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64SystemOperands.td
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Expand Up @@ -1722,7 +1722,7 @@ def : ROSysReg<"CNTVCTSS_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b110>;
}

// v8.7a LD64B/ST64B Accelerator Extension system register
let Requires = [{ {AArch64::FeatureLS64} }] in
let Requires = [{ {AArch64::FeatureLS64_ACCDATA} }] in
def : RWSysReg<"ACCDATA_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b101>;

// Branch Record Buffer system registers
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4 changes: 3 additions & 1 deletion llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
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Expand Up @@ -3681,7 +3681,9 @@ static const struct Extension {
{"sve2-sha3", {AArch64::FeatureSVE2SHA3}},
{"sve2-bitperm", {AArch64::FeatureSVE2BitPerm}},
{"sve2p1", {AArch64::FeatureSVE2p1}},
{"ls64", {AArch64::FeatureLS64}},
{"ls64",
{AArch64::FeatureLS64, AArch64::FeatureLS64_V,
AArch64::FeatureLS64_ACCDATA}},
{"xs", {AArch64::FeatureXS}},
{"pauth", {AArch64::FeaturePAuth}},
{"flagm", {AArch64::FeatureFlagM}},
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8 changes: 8 additions & 0 deletions llvm/lib/TargetParser/AArch64TargetParser.cpp
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Expand Up @@ -253,6 +253,14 @@ void AArch64::ExtensionSet::disable(ArchExtKind E) {
disable(AEK_SM4);
}

// FEAT_LS64, FEAT_LS64_V and FEAT_LS64_ACCDATA were historically lumped under
// the name 'ls64'. Therefore 'nols64' should disable all three even though
// their dependencies are not transitive.
if (E == AEK_LS64_ACCDATA) {
disable(AEK_LS64_V);
disable(AEK_LS64);
}

if (!Enabled.test(E))
return;

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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/ls64-intrinsics.ll
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@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64 -mattr=+ls64 -verify-machineinstrs -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64_be -mattr=+ls64 -verify-machineinstrs -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64 -mattr=+ls64_accdata -verify-machineinstrs -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64_be -mattr=+ls64_accdata -verify-machineinstrs -o - %s | FileCheck %s

define void @test_ld64b(ptr %out, ptr %addr) {
; CHECK-LABEL: test_ld64b:
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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/armv8.7a-ls64.s
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@@ -1,4 +1,4 @@
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+ls64 < %s 2>%t | FileCheck %s
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+ls64_accdata < %s 2>%t | FileCheck %s
// RUN: FileCheck --check-prefix=CHECK-ERR %s < %t
// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t
// RUN: FileCheck --check-prefixes=CHECK-ERR,CHECK-NO-LS64-ERR %s < %t
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