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[AArch64] Guard against non-vector abd long nodes. #102026

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Merged
merged 1 commit into from
Aug 6, 2024
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[AArch64] Guard against non-vector abd long nodes. #102026

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1 change: 1 addition & 0 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -21769,6 +21769,7 @@ static SDValue performExtendCombine(SDNode *N,
// helps the backend to decide that an sabdl2 would be useful, saving a real
// extract_high operation.
if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
N->getOperand(0).getValueType().is64BitVector() &&
(N->getOperand(0).getOpcode() == ISD::ABDU ||
N->getOperand(0).getOpcode() == ISD::ABDS)) {
SDNode *ABDNode = N->getOperand(0).getNode();
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22 changes: 22 additions & 0 deletions llvm/test/CodeGen/AArch64/abds.ll
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Expand Up @@ -571,6 +571,28 @@ define i32 @abd_sub_i32(i32 %a, i32 %b) nounwind {
ret i32 %abs
}

define i64 @vector_legalized(i16 %a, i16 %b) {
; CHECK-LABEL: vector_legalized:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: sxth w8, w0
; CHECK-NEXT: sub w8, w8, w1, sxth
; CHECK-NEXT: addp d0, v0.2d
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: cneg w8, w8, mi
; CHECK-NEXT: fmov x9, d0
; CHECK-NEXT: add x0, x9, x8
; CHECK-NEXT: ret
%ea = sext i16 %a to i32
%eb = sext i16 %b to i32
%s = sub i32 %ea, %eb
%ab = call i32 @llvm.abs.i32(i32 %s, i1 false)
%e = zext i32 %ab to i64
%red = call i64 @llvm.vector.reduce.add.v32i64(<32 x i64> zeroinitializer)
%z = add i64 %red, %e
ret i64 %z
}


declare i8 @llvm.abs.i8(i8, i1)
declare i16 @llvm.abs.i16(i16, i1)
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26 changes: 26 additions & 0 deletions llvm/test/CodeGen/AArch64/abdu.ll
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Expand Up @@ -409,6 +409,32 @@ define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
ret i128 %sel
}

;
; negative tests
;

define i64 @vector_legalized(i16 %a, i16 %b) {
; CHECK-LABEL: vector_legalized:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: sub w8, w8, w1, uxth
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: addp d0, v0.2d
; CHECK-NEXT: cneg w8, w8, mi
; CHECK-NEXT: fmov x9, d0
; CHECK-NEXT: add x0, x9, x8
; CHECK-NEXT: ret
%ea = zext i16 %a to i32
%eb = zext i16 %b to i32
%s = sub i32 %ea, %eb
%ab = call i32 @llvm.abs.i32(i32 %s, i1 false)
%e = zext i32 %ab to i64
%red = call i64 @llvm.vector.reduce.add.v32i64(<32 x i64> zeroinitializer)
%z = add i64 %red, %e
ret i64 %z
}

declare i8 @llvm.abs.i8(i8, i1)
declare i16 @llvm.abs.i16(i16, i1)
declare i32 @llvm.abs.i32(i32, i1)
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