Skip to content

[CodeGen] Allocate RegAllocHints map lazily #102186

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Aug 7, 2024
Merged

[CodeGen] Allocate RegAllocHints map lazily #102186

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
11 changes: 8 additions & 3 deletions llvm/include/llvm/CodeGen/MachineRegisterInfo.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -801,6 +801,7 @@ class MachineRegisterInfo {
/// of an earlier hint it will be overwritten.
void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg) {
assert(VReg.isVirtual());
RegAllocHints.grow(Register::index2VirtReg(getNumVirtRegs()));
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Should this be getNumVirtRegs() - 1? grow expects an index. getNumVRegs() is one past the largest index. Or maybe we could use resize?

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Good catch, opened #102273

RegAllocHints[VReg].first = Type;
RegAllocHints[VReg].second.clear();
RegAllocHints[VReg].second.push_back(PrefReg);
Expand All @@ -810,6 +811,7 @@ class MachineRegisterInfo {
/// vector for VReg.
void addRegAllocationHint(Register VReg, Register PrefReg) {
assert(VReg.isVirtual());
RegAllocHints.grow(Register::index2VirtReg(getNumVirtRegs()));
RegAllocHints[VReg].second.push_back(PrefReg);
}

Expand All @@ -822,14 +824,17 @@ class MachineRegisterInfo {
void clearSimpleHint(Register VReg) {
assert (!RegAllocHints[VReg].first &&
"Expected to clear a non-target hint!");
RegAllocHints[VReg].second.clear();
if (RegAllocHints.inBounds(VReg))
RegAllocHints[VReg].second.clear();
}

/// getRegAllocationHint - Return the register allocation hint for the
/// specified virtual register. If there are many hints, this returns the
/// one with the greatest weight.
std::pair<unsigned, Register> getRegAllocationHint(Register VReg) const {
assert(VReg.isVirtual());
if (!RegAllocHints.inBounds(VReg))
return {0, Register()};
Register BestHint = (RegAllocHints[VReg.id()].second.size() ?
RegAllocHints[VReg.id()].second[0] : Register());
return {RegAllocHints[VReg.id()].first, BestHint};
Expand All @@ -845,10 +850,10 @@ class MachineRegisterInfo {

/// getRegAllocationHints - Return a reference to the vector of all
/// register allocation hints for VReg.
const std::pair<unsigned, SmallVector<Register, 4>> &
const std::pair<unsigned, SmallVector<Register, 4>> *
getRegAllocationHints(Register VReg) const {
assert(VReg.isVirtual());
return RegAllocHints[VReg];
return RegAllocHints.inBounds(VReg) ? &RegAllocHints[VReg] : nullptr;
}

/// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
Expand Down
2 changes: 0 additions & 2 deletions llvm/lib/CodeGen/MachineRegisterInfo.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -47,7 +47,6 @@ MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF)
: MF->getSubtarget().enableSubRegLiveness()) {
unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
VRegInfo.reserve(256);
RegAllocHints.reserve(256);
UsedPhysRegMask.resize(NumRegs);
PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]());
TheDelegates.clear();
Expand Down Expand Up @@ -147,7 +146,6 @@ MachineRegisterInfo::recomputeRegClass(Register Reg) {
Register MachineRegisterInfo::createIncompleteVirtualRegister(StringRef Name) {
Register Reg = Register::index2VirtReg(getNumVirtRegs());
VRegInfo.grow(Reg);
RegAllocHints.grow(Reg);
insertVRegByName(Name, Reg);
return Reg;
}
Expand Down
9 changes: 6 additions & 3 deletions llvm/lib/CodeGen/TargetRegisterInfo.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -421,13 +421,16 @@ bool TargetRegisterInfo::getRegAllocationHints(
SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF,
const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
const MachineRegisterInfo &MRI = MF.getRegInfo();
const std::pair<unsigned, SmallVector<Register, 4>> &Hints_MRI =
const std::pair<unsigned, SmallVector<Register, 4>> *Hints_MRI =
MRI.getRegAllocationHints(VirtReg);

if (!Hints_MRI)
return false;

SmallSet<Register, 32> HintedRegs;
// First hint may be a target hint.
bool Skip = (Hints_MRI.first != 0);
for (auto Reg : Hints_MRI.second) {
bool Skip = (Hints_MRI->first != 0);
for (auto Reg : Hints_MRI->second) {
if (Skip) {
Skip = false;
continue;
Expand Down
10 changes: 6 additions & 4 deletions llvm/tools/llvm-reduce/ReducerWorkItem.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -306,9 +306,10 @@ static std::unique_ptr<MachineFunction> cloneMF(MachineFunction *SrcMF,
DstMRI->setType(NewReg, RegTy);

// Copy register allocation hints.
const auto &Hints = SrcMRI->getRegAllocationHints(Reg);
for (Register PrefReg : Hints.second)
DstMRI->addRegAllocationHint(NewReg, PrefReg);
const auto *Hints = SrcMRI->getRegAllocationHints(Reg);
if (Hints)
for (Register PrefReg : Hints->second)
DstMRI->addRegAllocationHint(NewReg, PrefReg);
}

const TargetSubtargetInfo &STI = DstMF->getSubtarget();
Expand Down Expand Up @@ -530,7 +531,8 @@ static uint64_t computeMIRComplexityScoreImpl(const MachineFunction &MF) {
const MachineRegisterInfo &MRI = MF.getRegInfo();
for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
Register Reg = Register::index2VirtReg(I);
Score += MRI.getRegAllocationHints(Reg).second.size();
if (const auto *Hints = MRI.getRegAllocationHints(Reg))
Score += Hints->second.size();
}

for (const MachineBasicBlock &MBB : MF) {
Expand Down
4 changes: 2 additions & 2 deletions llvm/tools/llvm-reduce/deltas/ReduceVirtualRegisters.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -23,9 +23,9 @@ static void dropRegisterHintsFromFunction(Oracle &O, MachineFunction &MF) {
for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
Register Reg = Register::index2VirtReg(I);

const std::pair<unsigned, SmallVector<Register, 4>> &Hints =
const std::pair<unsigned, SmallVector<Register, 4>> *Hints =
MRI.getRegAllocationHints(Reg);
if (Hints.second.empty())
if (!Hints || Hints->second.empty())
continue;

if (!O.shouldKeep())
Expand Down
Loading