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[RISCV] Use listconcat to shorten some of the profile feature lists. #102356

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Aug 8, 2024
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[RISCV] Use listconcat to shorten some of the profile feature lists. #102356

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264 changes: 113 additions & 151 deletions llvm/lib/Target/RISCV/RISCVProfiles.td
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Original file line number Diff line number Diff line change
Expand Up @@ -6,169 +6,113 @@
//
//===----------------------------------------------------------------------===//

class RISCVProfile<string name, list<SubtargetFeature> features>
: SubtargetFeature<name, "Is" # NAME, "true",
"RISC-V " # name # " profile", features> {
// Indicates if the profile is not yet ratified, so should be treated as
// experimental.
bit Experimental = false;
}
class RISCVExperimentalProfile<string name, list<SubtargetFeature> features>
: RISCVProfile<"experimental-"#name, features> {
let Experimental = true;
}
//===----------------------------------------------------------------------===//
// Profile Featuyre Lists
//===----------------------------------------------------------------------===//

// RVI Profile Family

defvar RVI20U32Features = [Feature32Bit, FeatureStdExtI];
defvar RVI20U64Features = [Feature64Bit, FeatureStdExtI];

defvar RVA20U64Features = [Feature64Bit,
FeatureStdExtI,
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC,
FeatureStdExtZicntr,
FeatureStdExtZiccif,
FeatureStdExtZiccrse,
FeatureStdExtZiccamoa,
FeatureStdExtZa128rs,
FeatureStdExtZicclsm];
// RVA Profile Family

defvar RVA20U64BaseFeatures = [Feature64Bit,
FeatureStdExtI,
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC,
FeatureStdExtZicntr,
FeatureStdExtZiccif,
FeatureStdExtZiccrse,
FeatureStdExtZiccamoa,
FeatureStdExtZicclsm];
defvar RVA20U64Features = !listconcat(RVA20U64BaseFeatures,
[FeatureStdExtZa128rs]);

defvar RVA20S64BaseFeatures = [FeatureStdExtZifencei,
FeatureStdExtSvbare,
FeatureStdExtSvade,
FeatureStdExtSsccptr,
FeatureStdExtSstvecd,
FeatureStdExtSstvala];
defvar RVA20S64Features = !listconcat(RVA20U64Features,
[FeatureStdExtZifencei,
FeatureStdExtSvbare,
FeatureStdExtSvade,
FeatureStdExtSsccptr,
FeatureStdExtSstvecd,
FeatureStdExtSstvala]);
RVA20S64BaseFeatures);

defvar RVA22U64Features = [Feature64Bit,
FeatureStdExtI,
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC,
FeatureStdExtZicntr,
FeatureStdExtZiccif,
FeatureStdExtZiccrse,
FeatureStdExtZiccamoa,
FeatureStdExtZicclsm,
FeatureStdExtZa64rs,
FeatureStdExtZihpm,
FeatureStdExtZihintpause,
FeatureStdExtZba,
FeatureStdExtZbb,
FeatureStdExtZbs,
FeatureStdExtZic64b,
FeatureStdExtZicbom,
FeatureStdExtZicbop,
FeatureStdExtZicboz,
FeatureStdExtZfhmin,
FeatureStdExtZkt];
defvar RVA22U64Features = !listconcat(RVA20U64BaseFeatures,
[FeatureStdExtZa64rs,
FeatureStdExtZihpm,
FeatureStdExtZihintpause,
FeatureStdExtZba,
FeatureStdExtZbb,
FeatureStdExtZbs,
FeatureStdExtZic64b,
FeatureStdExtZicbom,
FeatureStdExtZicbop,
FeatureStdExtZicboz,
FeatureStdExtZfhmin,
FeatureStdExtZkt]);

defvar RVA22S64BaseFeatures = !listconcat(RVA20S64BaseFeatures,
[FeatureStdExtSscounterenw,
FeatureStdExtSvpbmt,
FeatureStdExtSvinval]);
defvar RVA22S64Features = !listconcat(RVA22U64Features,
[FeatureStdExtZifencei,
FeatureStdExtSvbare,
FeatureStdExtSvade,
FeatureStdExtSsccptr,
FeatureStdExtSstvecd,
FeatureStdExtSstvala,
FeatureStdExtSscounterenw,
FeatureStdExtSvpbmt,
FeatureStdExtSvinval]);
RVA22S64BaseFeatures);

defvar RVA23U64Features = [Feature64Bit,
FeatureStdExtI,
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC,
FeatureStdExtZicntr,
FeatureStdExtZihpm,
FeatureStdExtZiccif,
FeatureStdExtZiccrse,
FeatureStdExtZiccamoa,
FeatureStdExtZicclsm,
FeatureStdExtZa64rs,
FeatureStdExtZihintpause,
FeatureStdExtZba,
FeatureStdExtZbb,
FeatureStdExtZbs,
FeatureStdExtZic64b,
FeatureStdExtZicbom,
FeatureStdExtZicbop,
FeatureStdExtZicboz,
FeatureStdExtZfhmin,
FeatureStdExtZkt,
FeatureStdExtV,
FeatureStdExtZvfhmin,
FeatureStdExtZvbb,
FeatureStdExtZvkt,
FeatureStdExtZihintntl,
FeatureStdExtZicond,
FeatureStdExtZimop,
FeatureStdExtZcmop,
FeatureStdExtZcb,
FeatureStdExtZfa,
FeatureStdExtZawrs];
defvar RVA23U64Features = !listconcat(RVA22U64Features,
[FeatureStdExtV,
FeatureStdExtZvfhmin,
FeatureStdExtZvbb,
FeatureStdExtZvkt,
FeatureStdExtZihintntl,
FeatureStdExtZicond,
FeatureStdExtZimop,
FeatureStdExtZcmop,
FeatureStdExtZcb,
FeatureStdExtZfa,
FeatureStdExtZawrs]);

defvar RVA23S64BaseFeatures = !listconcat(RVA22S64BaseFeatures,
[FeatureStdExtSvnapot,
FeatureStdExtSstc,
FeatureStdExtSscofpmf,
FeatureStdExtSsnpm,
FeatureStdExtSsu64xl,
FeatureStdExtH,
FeatureStdExtSsstateen,
FeatureStdExtShcounterenw,
FeatureStdExtShvstvala,
FeatureStdExtShtvala,
FeatureStdExtShvstvecd,
FeatureStdExtShvsatpa,
FeatureStdExtShgatpa]);
defvar RVA23S64Features = !listconcat(RVA23U64Features,
[FeatureStdExtZifencei,
FeatureStdExtSvbare,
FeatureStdExtSvade,
FeatureStdExtSsccptr,
FeatureStdExtSstvecd,
FeatureStdExtSstvala,
FeatureStdExtSscounterenw,
FeatureStdExtSvpbmt,
FeatureStdExtSvinval,
FeatureStdExtSvnapot,
FeatureStdExtSstc,
FeatureStdExtSscofpmf,
FeatureStdExtSsnpm,
FeatureStdExtSsu64xl,
FeatureStdExtH,
FeatureStdExtSsstateen,
FeatureStdExtShcounterenw,
FeatureStdExtShvstvala,
FeatureStdExtShtvala,
FeatureStdExtShvstvecd,
FeatureStdExtShvsatpa,
FeatureStdExtShgatpa]);

defvar RVB23U64Features = [Feature64Bit,
FeatureStdExtI,
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC,
FeatureStdExtZicntr,
FeatureStdExtZihpm,
FeatureStdExtZiccif,
FeatureStdExtZiccrse,
FeatureStdExtZiccamoa,
FeatureStdExtZicclsm,
FeatureStdExtZa64rs,
FeatureStdExtZihintpause,
FeatureStdExtZba,
FeatureStdExtZbb,
FeatureStdExtZbs,
FeatureStdExtZic64b,
FeatureStdExtZicbom,
FeatureStdExtZicbop,
FeatureStdExtZicboz,
FeatureStdExtZkt,
FeatureStdExtZihintntl,
FeatureStdExtZicond,
FeatureStdExtZimop,
FeatureStdExtZcmop,
FeatureStdExtZcb,
FeatureStdExtZfa,
FeatureStdExtZawrs];
RVA23S64BaseFeatures);

// RVB Profile Family

defvar RVB23U64Features = !listconcat(RVA20U64BaseFeatures,
[FeatureStdExtZihpm,
FeatureStdExtZa64rs,
FeatureStdExtZihintpause,
FeatureStdExtZba,
FeatureStdExtZbb,
FeatureStdExtZbs,
FeatureStdExtZic64b,
FeatureStdExtZicbom,
FeatureStdExtZicbop,
FeatureStdExtZicboz,
FeatureStdExtZkt,
FeatureStdExtZihintntl,
FeatureStdExtZicond,
FeatureStdExtZimop,
FeatureStdExtZcmop,
FeatureStdExtZcb,
FeatureStdExtZfa,
FeatureStdExtZawrs]);

defvar RVB23S64Features = !listconcat(RVB23U64Features,
[FeatureStdExtZifencei,
Expand All @@ -185,6 +129,8 @@ defvar RVB23S64Features = !listconcat(RVB23U64Features,
FeatureStdExtSscofpmf,
FeatureStdExtSsu64xl]);

// RVM Profile Family

defvar RVM23U32Features = [Feature32Bit,
FeatureStdExtI,
FeatureStdExtM,
Expand All @@ -199,6 +145,22 @@ defvar RVM23U32Features = [Feature32Bit,
FeatureStdExtZimop,
FeatureStdExtZcmop];

//===----------------------------------------------------------------------===//
// Profile Definitions for ISA String
//===----------------------------------------------------------------------===//

class RISCVProfile<string name, list<SubtargetFeature> features>
: SubtargetFeature<name, "Is" # NAME, "true",
"RISC-V " # name # " profile", features> {
// Indicates if the profile is not yet ratified, so should be treated as
// experimental.
bit Experimental = false;
}
class RISCVExperimentalProfile<string name, list<SubtargetFeature> features>
: RISCVProfile<"experimental-"#name, features> {
let Experimental = true;
}

def RVI20U32 : RISCVProfile<"rvi20u32", RVI20U32Features>;
def RVI20U64 : RISCVProfile<"rvi20u64", RVI20U64Features>;
def RVA20U64 : RISCVProfile<"rva20u64", RVA20U64Features>;
Expand Down
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