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[RISCV][GISel] Remove s32 support on RV64 for DIV, and REM. #102519

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Merged
merged 1 commit into from
Aug 20, 2024
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[RISCV][GISel] Remove s32 support on RV64 for DIV, and REM. #102519

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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -396,9 +396,9 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)

if (ST.hasStdExtM()) {
getActionDefinitionsBuilder({G_UDIV, G_SDIV, G_UREM, G_SREM})
.legalFor({s32, sXLen})
.legalFor({sXLen})
.libcallFor({sDoubleXLen})
.clampScalar(0, s32, sDoubleXLen)
.clampScalar(0, sXLen, sDoubleXLen)
.widenScalarToNextPow2(0);
} else {
getActionDefinitionsBuilder({G_UDIV, G_SDIV, G_UREM, G_SREM})
Expand Down
20 changes: 16 additions & 4 deletions llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -348,7 +348,9 @@ define i32 @sdiv_i32(i32 %a, i32 %b) {
;
; RV64IM-LABEL: sdiv_i32:
; RV64IM: # %bb.0: # %entry
; RV64IM-NEXT: divw a0, a0, a1
; RV64IM-NEXT: sext.w a0, a0
; RV64IM-NEXT: sext.w a1, a1
; RV64IM-NEXT: div a0, a0, a1
; RV64IM-NEXT: ret
entry:
%0 = sdiv i32 %a, %b
Expand All @@ -363,7 +365,9 @@ define i32 @srem_i32(i32 %a, i32 %b) {
;
; RV64IM-LABEL: srem_i32:
; RV64IM: # %bb.0: # %entry
; RV64IM-NEXT: remw a0, a0, a1
; RV64IM-NEXT: sext.w a0, a0
; RV64IM-NEXT: sext.w a1, a1
; RV64IM-NEXT: rem a0, a0, a1
; RV64IM-NEXT: ret
entry:
%0 = srem i32 %a, %b
Expand All @@ -378,7 +382,11 @@ define i32 @udiv_i32(i32 %a, i32 %b) {
;
; RV64IM-LABEL: udiv_i32:
; RV64IM: # %bb.0: # %entry
; RV64IM-NEXT: divuw a0, a0, a1
; RV64IM-NEXT: slli a0, a0, 32
; RV64IM-NEXT: srli a0, a0, 32
; RV64IM-NEXT: slli a1, a1, 32
; RV64IM-NEXT: srli a1, a1, 32
; RV64IM-NEXT: divu a0, a0, a1
; RV64IM-NEXT: ret
entry:
%0 = udiv i32 %a, %b
Expand All @@ -393,7 +401,11 @@ define i32 @urem_i32(i32 %a, i32 %b) {
;
; RV64IM-LABEL: urem_i32:
; RV64IM: # %bb.0: # %entry
; RV64IM-NEXT: remuw a0, a0, a1
; RV64IM-NEXT: slli a0, a0, 32
; RV64IM-NEXT: srli a0, a0, 32
; RV64IM-NEXT: slli a1, a1, 32
; RV64IM-NEXT: srli a1, a1, 32
; RV64IM-NEXT: remu a0, a0, a1
; RV64IM-NEXT: ret
entry:
%0 = urem i32 %a, %b
Expand Down
135 changes: 0 additions & 135 deletions llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -2,141 +2,6 @@
# RUN: llc -mtriple=riscv64 -mattr=+m -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
# RUN: | FileCheck -check-prefix=RV64I %s

---
name: mul_i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $x11

; RV64I-LABEL: name: mul_i32
; RV64I: liveins: $x10, $x11
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
; RV64I-NEXT: [[MULW:%[0-9]+]]:gpr = MULW [[COPY]], [[COPY1]]
; RV64I-NEXT: $x10 = COPY [[MULW]]
; RV64I-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = COPY $x10
%1:gprb(s32) = G_TRUNC %0(s64)
%2:gprb(s64) = COPY $x11
%3:gprb(s32) = G_TRUNC %2(s64)
%4:gprb(s32) = G_MUL %1, %3
%5:gprb(s64) = G_ANYEXT %4(s32)
$x10 = COPY %5(s64)
PseudoRET implicit $x10

...
---
name: sdiv_i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $x11

; RV64I-LABEL: name: sdiv_i32
; RV64I: liveins: $x10, $x11
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
; RV64I-NEXT: [[DIVW:%[0-9]+]]:gpr = DIVW [[COPY]], [[COPY1]]
; RV64I-NEXT: $x10 = COPY [[DIVW]]
; RV64I-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = COPY $x10
%1:gprb(s32) = G_TRUNC %0(s64)
%2:gprb(s64) = COPY $x11
%3:gprb(s32) = G_TRUNC %2(s64)
%4:gprb(s32) = G_SDIV %1, %3
%5:gprb(s64) = G_ANYEXT %4(s32)
$x10 = COPY %5(s64)
PseudoRET implicit $x10

...
---
name: srem_i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $x11

; RV64I-LABEL: name: srem_i32
; RV64I: liveins: $x10, $x11
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
; RV64I-NEXT: [[REMW:%[0-9]+]]:gpr = REMW [[COPY]], [[COPY1]]
; RV64I-NEXT: $x10 = COPY [[REMW]]
; RV64I-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = COPY $x10
%1:gprb(s32) = G_TRUNC %0(s64)
%2:gprb(s64) = COPY $x11
%3:gprb(s32) = G_TRUNC %2(s64)
%4:gprb(s32) = G_SREM %1, %3
%5:gprb(s64) = G_ANYEXT %4(s32)
$x10 = COPY %5(s64)
PseudoRET implicit $x10

...
---
name: udiv_i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $x11

; RV64I-LABEL: name: udiv_i32
; RV64I: liveins: $x10, $x11
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
; RV64I-NEXT: [[DIVUW:%[0-9]+]]:gpr = DIVUW [[COPY]], [[COPY1]]
; RV64I-NEXT: $x10 = COPY [[DIVUW]]
; RV64I-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = COPY $x10
%1:gprb(s32) = G_TRUNC %0(s64)
%2:gprb(s64) = COPY $x11
%3:gprb(s32) = G_TRUNC %2(s64)
%4:gprb(s32) = G_UDIV %1, %3
%5:gprb(s64) = G_ANYEXT %4(s32)
$x10 = COPY %5(s64)
PseudoRET implicit $x10

...
---
name: urem_i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $x11

; RV64I-LABEL: name: urem_i32
; RV64I: liveins: $x10, $x11
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
; RV64I-NEXT: [[REMUW:%[0-9]+]]:gpr = REMUW [[COPY]], [[COPY1]]
; RV64I-NEXT: $x10 = COPY [[REMUW]]
; RV64I-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = COPY $x10
%1:gprb(s32) = G_TRUNC %0(s64)
%2:gprb(s64) = COPY $x11
%3:gprb(s32) = G_TRUNC %2(s64)
%4:gprb(s32) = G_UREM %1, %3
%5:gprb(s64) = G_ANYEXT %4(s32)
$x10 = COPY %5(s64)
PseudoRET implicit $x10

...
---
name: mul_i64
legalized: true
Expand Down
128 changes: 52 additions & 76 deletions llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv64.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -28,19 +28,14 @@ body: |
; CHECK-M-LABEL: name: sdiv_i8
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s64)
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s64)
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-M-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C2]](s64)
; CHECK-M-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C3]](s64)
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SDIV]](s32)
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[ASHR]], [[ASHR1]]
; CHECK-M-NEXT: $x10 = COPY [[SDIV]](s64)
; CHECK-M-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
Expand Down Expand Up @@ -77,19 +72,14 @@ body: |
; CHECK-M-LABEL: name: sdiv_i15
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 17
; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s64)
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 17
; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s64)
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-M-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 17
; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C2]](s64)
; CHECK-M-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 17
; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C3]](s64)
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SDIV]](s32)
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 49
; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 49
; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[ASHR]], [[ASHR1]]
; CHECK-M-NEXT: $x10 = COPY [[SDIV]](s64)
; CHECK-M-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
Expand Down Expand Up @@ -126,19 +116,14 @@ body: |
; CHECK-M-LABEL: name: sdiv_i16
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s64)
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s64)
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-M-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C2]](s64)
; CHECK-M-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C3]](s64)
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SDIV]](s32)
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[ASHR]], [[ASHR1]]
; CHECK-M-NEXT: $x10 = COPY [[SDIV]](s64)
; CHECK-M-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
Expand Down Expand Up @@ -171,11 +156,10 @@ body: |
; CHECK-M-LABEL: name: sdiv_i32
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[TRUNC]], [[TRUNC1]]
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SDIV]](s32)
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
; CHECK-M-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
; CHECK-M-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK-M-NEXT: $x10 = COPY [[SDIV]](s64)
; CHECK-M-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
Expand Down Expand Up @@ -358,15 +342,12 @@ body: |
; CHECK-M-LABEL: name: udiv_i8
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UDIV]](s32)
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[AND]], [[AND1]]
; CHECK-M-NEXT: $x10 = COPY [[UDIV]](s64)
; CHECK-M-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
Expand Down Expand Up @@ -401,15 +382,12 @@ body: |
; CHECK-M-LABEL: name: udiv_i15
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UDIV]](s32)
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767
; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767
; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[AND]], [[AND1]]
; CHECK-M-NEXT: $x10 = COPY [[UDIV]](s64)
; CHECK-M-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
Expand Down Expand Up @@ -444,15 +422,12 @@ body: |
; CHECK-M-LABEL: name: udiv_i16
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UDIV]](s32)
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[AND]], [[AND1]]
; CHECK-M-NEXT: $x10 = COPY [[UDIV]](s64)
; CHECK-M-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
Expand Down Expand Up @@ -487,11 +462,12 @@ body: |
; CHECK-M-LABEL: name: udiv_i32
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[TRUNC]], [[TRUNC1]]
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UDIV]](s32)
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[AND]], [[AND1]]
; CHECK-M-NEXT: $x10 = COPY [[UDIV]](s64)
; CHECK-M-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
Expand Down
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