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[AMDGPU][AsmParser] Eliminate validateExeczVcczOperands(). #102600

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Merged
merged 1 commit into from
Aug 12, 2024
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[AMDGPU][AsmParser] Eliminate validateExeczVcczOperands(). #102600

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77 changes: 30 additions & 47 deletions llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1777,7 +1777,6 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
const SMLoc &IDLoc);
bool validateTHAndScopeBits(const MCInst &Inst, const OperandVector &Operands,
const unsigned CPol);
bool validateExeczVcczOperands(const OperandVector &Operands);
bool validateTFE(const MCInst &Inst, const OperandVector &Operands);
std::optional<StringRef> validateLdsDirect(const MCInst &Inst);
unsigned getConstantBusLimit(unsigned Opcode) const;
Expand Down Expand Up @@ -3039,7 +3038,8 @@ bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,
if (Reg == AMDGPU::SGPR_NULL) {
Error(Loc, "'null' operand is not supported on this GPU");
} else {
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This else is probably not needed, Error shall act like a return.

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Actually it does not return, but can be used as return Error() instead.

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MCAsmParser::Error() seems to return true, so wouldn't work. (Confusingly, our AMDGPUAsmParser::Error() returns false, but from what I see that's not what we call here.)

Error(Loc, "register not available on this GPU");
Error(Loc, Twine(AMDGPUInstPrinter::getRegisterName(Reg)) +
" register not available on this GPU");
}
return false;
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... and this line is dead.

}
Expand Down Expand Up @@ -5052,22 +5052,6 @@ bool AMDGPUAsmParser::validateTHAndScopeBits(const MCInst &Inst,
return true;
}

bool AMDGPUAsmParser::validateExeczVcczOperands(const OperandVector &Operands) {
if (!isGFX11Plus())
return true;
for (auto &Operand : Operands) {
if (!Operand->isReg())
continue;
unsigned Reg = Operand->getReg();
if (Reg == SRC_EXECZ || Reg == SRC_VCCZ) {
Error(getRegLoc(Reg, Operands),
"execz and vccz are not supported on this GPU");
return false;
}
}
return true;
}

bool AMDGPUAsmParser::validateTFE(const MCInst &Inst,
const OperandVector &Operands) {
const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
Expand Down Expand Up @@ -5203,9 +5187,6 @@ bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
if (!validateWaitCnt(Inst, Operands)) {
return false;
}
if (!validateExeczVcczOperands(Operands)) {
return false;
}
if (!validateTFE(Inst, Operands)) {
return false;
}
Expand Down Expand Up @@ -6247,39 +6228,41 @@ bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {

bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
unsigned RegNo) {

if (MRI.regsOverlap(AMDGPU::TTMP12_TTMP13_TTMP14_TTMP15, RegNo))
if (MRI.regsOverlap(TTMP12_TTMP13_TTMP14_TTMP15, RegNo))
return isGFX9Plus();

// GFX10+ has 2 more SGPRs 104 and 105.
if (MRI.regsOverlap(AMDGPU::SGPR104_SGPR105, RegNo))
if (MRI.regsOverlap(SGPR104_SGPR105, RegNo))
return hasSGPR104_SGPR105();

switch (RegNo) {
case AMDGPU::SRC_SHARED_BASE_LO:
case AMDGPU::SRC_SHARED_BASE:
case AMDGPU::SRC_SHARED_LIMIT_LO:
case AMDGPU::SRC_SHARED_LIMIT:
case AMDGPU::SRC_PRIVATE_BASE_LO:
case AMDGPU::SRC_PRIVATE_BASE:
case AMDGPU::SRC_PRIVATE_LIMIT_LO:
case AMDGPU::SRC_PRIVATE_LIMIT:
case SRC_SHARED_BASE_LO:
case SRC_SHARED_BASE:
case SRC_SHARED_LIMIT_LO:
case SRC_SHARED_LIMIT:
case SRC_PRIVATE_BASE_LO:
case SRC_PRIVATE_BASE:
case SRC_PRIVATE_LIMIT_LO:
case SRC_PRIVATE_LIMIT:
return isGFX9Plus();
case AMDGPU::SRC_POPS_EXITING_WAVE_ID:
case SRC_POPS_EXITING_WAVE_ID:
return isGFX9Plus() && !isGFX11Plus();
case AMDGPU::TBA:
case AMDGPU::TBA_LO:
case AMDGPU::TBA_HI:
case AMDGPU::TMA:
case AMDGPU::TMA_LO:
case AMDGPU::TMA_HI:
case TBA:
case TBA_LO:
case TBA_HI:
case TMA:
case TMA_LO:
case TMA_HI:
return !isGFX9Plus();
case AMDGPU::XNACK_MASK:
case AMDGPU::XNACK_MASK_LO:
case AMDGPU::XNACK_MASK_HI:
case XNACK_MASK:
case XNACK_MASK_LO:
case XNACK_MASK_HI:
return (isVI() || isGFX9()) && getTargetStreamer().getTargetID()->isXnackSupported();
case AMDGPU::SGPR_NULL:
case SGPR_NULL:
return isGFX10Plus();
case SRC_EXECZ:
case SRC_VCCZ:
return !isGFX11Plus();
default:
break;
}
Expand All @@ -6292,9 +6275,9 @@ bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
// On GFX10Plus flat scratch is not a valid register operand and can only be
// accessed with s_setreg/s_getreg.
switch (RegNo) {
case AMDGPU::FLAT_SCR:
case AMDGPU::FLAT_SCR_LO:
case AMDGPU::FLAT_SCR_HI:
case FLAT_SCR:
case FLAT_SCR_LO:
case FLAT_SCR_HI:
return false;
default:
return true;
Expand All @@ -6303,7 +6286,7 @@ bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,

// VI only has 102 SGPRs, so make sure we aren't trying to use the 2 more that
// SI/CI have.
if (MRI.regsOverlap(AMDGPU::SGPR102_SGPR103, RegNo))
if (MRI.regsOverlap(SGPR102_SGPR103, RegNo))
return hasSGPR102_SGPR103();

return true;
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/MC/AMDGPU/expressions.s
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Original file line number Diff line number Diff line change
Expand Up @@ -337,4 +337,4 @@ v_sin_f32 v0, -s1000

xnack_mask_lo=1
v_sin_f32 v0, xnack_mask_lo
// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: register not available on this GPU
// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: xnack_mask_lo register not available on this GPU
12 changes: 6 additions & 6 deletions llvm/test/MC/AMDGPU/flat-scratch.s
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Original file line number Diff line number Diff line change
Expand Up @@ -5,32 +5,32 @@
// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=VI %s

s_mov_b64 flat_scratch, -1
// NOSI: :[[@LINE-1]]:{{[0-9]+}}: error: register not available on this GPU
// NOSI: :[[@LINE-1]]:{{[0-9]+}}: error: flat_scratch register not available on this GPU
// CI: s_mov_b64 flat_scratch, -1 ; encoding: [0xc1,0x04,0xe8,0xbe]
// VI: s_mov_b64 flat_scratch, -1 ; encoding: [0xc1,0x01,0xe6,0xbe]

s_mov_b32 flat_scratch_lo, -1
// NOSI: :[[@LINE-1]]:{{[0-9]+}}: error: register not available on this GPU
// NOSI: :[[@LINE-1]]:{{[0-9]+}}: error: flat_scratch_lo register not available on this GPU
// CI: s_mov_b32 flat_scratch_lo, -1 ; encoding: [0xc1,0x03,0xe8,0xbe]
// VI: s_mov_b32 flat_scratch_lo, -1 ; encoding: [0xc1,0x00,0xe6,0xbe]

s_mov_b32 flat_scratch_hi, -1
// NOSI: :[[@LINE-1]]:{{[0-9]+}}: error: register not available on this GPU
// NOSI: :[[@LINE-1]]:{{[0-9]+}}: error: flat_scratch_hi register not available on this GPU
// CI: s_mov_b32 flat_scratch_hi, -1 ; encoding: [0xc1,0x03,0xe9,0xbe]
// VI: s_mov_b32 flat_scratch_hi, -1 ; encoding: [0xc1,0x00,0xe7,0xbe]


s_mov_b64 flat_scratch_lo, -1
// NOSI: :[[@LINE-1]]:{{[0-9]+}}: error: register not available on this GPU
// NOSI: :[[@LINE-1]]:{{[0-9]+}}: error: flat_scratch_lo register not available on this GPU
// NOCI: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: invalid operand for instruction

s_mov_b64 flat_scratch_hi, -1
// NOSI: :[[@LINE-1]]:{{[0-9]+}}: error: register not available on this GPU
// NOSI: :[[@LINE-1]]:{{[0-9]+}}: error: flat_scratch_hi register not available on this GPU
// NOCI: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: invalid operand for instruction

s_mov_b32 flat_scratch, -1
// NOSI: :[[@LINE-1]]:{{[0-9]+}}: error: register not available on this GPU
// NOSI: :[[@LINE-1]]:{{[0-9]+}}: error: flat_scratch register not available on this GPU
// NOCI: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: invalid operand for instruction
4 changes: 2 additions & 2 deletions llvm/test/MC/AMDGPU/gfx10_err_pos.s
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Expand Up @@ -1124,12 +1124,12 @@ v_add_nc_i32 v256, v0, v1
// register not available on this GPU

s_and_b32 ttmp9, tma_hi, 0x0000ffff
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: register not available on this GPU
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: tma_hi register not available on this GPU
// CHECK-NEXT:{{^}}s_and_b32 ttmp9, tma_hi, 0x0000ffff
// CHECK-NEXT:{{^}} ^

s_mov_b32 flat_scratch, -1
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: register not available on this GPU
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: flat_scratch register not available on this GPU
// CHECK-NEXT:{{^}}s_mov_b32 flat_scratch, -1
// CHECK-NEXT:{{^}} ^

Expand Down
48 changes: 24 additions & 24 deletions llvm/test/MC/AMDGPU/gfx11_asm_operands.s
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Expand Up @@ -16,35 +16,35 @@ s_cbranch_execz 0x100

s_add_i32 s0, execz, s2
// GFX10: encoding: [0xfc,0x02,0x00,0x81]
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_execz register not available on this GPU

s_add_i32 s0, src_execz, s2
// GFX10: encoding: [0xfc,0x02,0x00,0x81]
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_execz register not available on this GPU

s_add_i32 s0, s1, execz
// GFX10: encoding: [0x01,0xfc,0x00,0x81]
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_execz register not available on this GPU

s_add_i32 s0, s1, src_execz
// GFX10: encoding: [0x01,0xfc,0x00,0x81]
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_execz register not available on this GPU

v_add_f64 v[0:1], execz, v[2:3]
// GFX10: encoding: [0x00,0x00,0x64,0xd5,0xfc,0x04,0x02,0x00]
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_execz register not available on this GPU

v_add_f64 v[0:1], src_execz, v[2:3]
// GFX10: encoding: [0x00,0x00,0x64,0xd5,0xfc,0x04,0x02,0x00]
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_execz register not available on this GPU

v_add_f64 v[0:1], v[1:2], execz
// GFX10: encoding: [0x00,0x00,0x64,0xd5,0x01,0xf9,0x01,0x00]
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_execz register not available on this GPU

v_add_f64 v[0:1], v[1:2], src_execz
// GFX10: encoding: [0x00,0x00,0x64,0xd5,0x01,0xf9,0x01,0x00]
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_execz register not available on this GPU

//---------------------------------------------------------------------------//
// VCCZ
Expand All @@ -56,35 +56,35 @@ s_cbranch_vccz 0x100

s_add_i32 s0, vccz, s2
// GFX10: encoding: [0xfb,0x02,0x00,0x81]
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_vccz register not available on this GPU

s_add_i32 s0, src_vccz, s2
// GFX10: encoding: [0xfb,0x02,0x00,0x81]
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_vccz register not available on this GPU

s_add_i32 s0, s1, vccz
// GFX10: encoding: [0x01,0xfb,0x00,0x81]
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_vccz register not available on this GPU

s_add_i32 s0, s1, src_vccz
// GFX10: encoding: [0x01,0xfb,0x00,0x81]
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_vccz register not available on this GPU

v_add_f64 v[0:1], vccz, v[2:3]
// GFX10: encoding: [0x00,0x00,0x64,0xd5,0xfb,0x04,0x02,0x00]
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_vccz register not available on this GPU

v_add_f64 v[0:1], src_vccz, v[2:3]
// GFX10: encoding: [0x00,0x00,0x64,0xd5,0xfb,0x04,0x02,0x00]
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_vccz register not available on this GPU

v_add_f64 v[0:1], v[1:2], vccz
// GFX10: encoding: [0x00,0x00,0x64,0xd5,0x01,0xf7,0x01,0x00]
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_vccz register not available on this GPU

v_add_f64 v[0:1], v[1:2], src_vccz
// GFX10: encoding: [0x00,0x00,0x64,0xd5,0x01,0xf7,0x01,0x00]
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_vccz register not available on this GPU

//---------------------------------------------------------------------------//
// LDS_DIRECT
Expand Down Expand Up @@ -112,32 +112,32 @@ v_mov_b32 v0, src_lds_direct

s_add_i32 s0, src_pops_exiting_wave_id, s1
// GFX10: encoding: [0xef,0x01,0x00,0x81]
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: register not available on this GPU
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_pops_exiting_wave_id register not available on this GPU

s_add_i32 s0, s1, src_pops_exiting_wave_id
// GFX10: encoding: [0x01,0xef,0x00,0x81]
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: register not available on this GPU
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_pops_exiting_wave_id register not available on this GPU

s_add_i32 s0, pops_exiting_wave_id, s1
// GFX10: encoding: [0xef,0x01,0x00,0x81]
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: register not available on this GPU
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_pops_exiting_wave_id register not available on this GPU

s_add_i32 s0, s1, pops_exiting_wave_id
// GFX10: encoding: [0x01,0xef,0x00,0x81]
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: register not available on this GPU
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_pops_exiting_wave_id register not available on this GPU

v_add_co_u32 v0, s0, pops_exiting_wave_id, v1
// GFX10: encoding: [0x00,0x00,0x0f,0xd7,0xef,0x02,0x02,0x00]
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: register not available on this GPU
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_pops_exiting_wave_id register not available on this GPU

v_add_co_u32 v0, s0, src_pops_exiting_wave_id, v1
// GFX10: encoding: [0x00,0x00,0x0f,0xd7,0xef,0x02,0x02,0x00]
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: register not available on this GPU
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_pops_exiting_wave_id register not available on this GPU

v_add_co_u32 v0, s0, v1, pops_exiting_wave_id
// GFX10: encoding: [0x00,0x00,0x0f,0xd7,0x01,0xdf,0x01,0x00]
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: register not available on this GPU
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_pops_exiting_wave_id register not available on this GPU

v_add_co_u32 v0, s0, v1, src_pops_exiting_wave_id
// GFX10: encoding: [0x00,0x00,0x0f,0xd7,0x01,0xdf,0x01,0x00]
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: register not available on this GPU
// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_pops_exiting_wave_id register not available on this GPU
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