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[RISCV] Simplify (srl (and X, Mask), Const) to TH_EXTU #102802

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Merged
merged 1 commit into from
Aug 16, 2024
Merged

[RISCV] Simplify (srl (and X, Mask), Const) to TH_EXTU #102802

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9 changes: 9 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1164,6 +1164,15 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
}

unsigned LShAmt = Subtarget->getXLen() - TrailingOnes;
if (Subtarget->hasVendorXTHeadBb()) {
SDNode *THEXTU = CurDAG->getMachineNode(
RISCV::TH_EXTU, DL, VT, N0->getOperand(0),
CurDAG->getTargetConstant(TrailingOnes - 1, DL, VT),
CurDAG->getTargetConstant(ShAmt, DL, VT));
ReplaceNode(Node, THEXTU);
return;
}

SDNode *SLLI =
CurDAG->getMachineNode(RISCV::SLLI, DL, VT, N0->getOperand(0),
CurDAG->getTargetConstant(LShAmt, DL, VT));
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14 changes: 6 additions & 8 deletions llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
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Expand Up @@ -2367,10 +2367,9 @@ define i16 @test_ctpop_i16(i16 %a) nounwind {
; RV32XTHEADBB-NEXT: add a0, a2, a0
; RV32XTHEADBB-NEXT: srli a1, a0, 4
; RV32XTHEADBB-NEXT: add a0, a0, a1
; RV32XTHEADBB-NEXT: andi a1, a0, 15
; RV32XTHEADBB-NEXT: slli a0, a0, 20
; RV32XTHEADBB-NEXT: srli a0, a0, 28
; RV32XTHEADBB-NEXT: add a0, a1, a0
; RV32XTHEADBB-NEXT: th.extu a1, a0, 11, 8
; RV32XTHEADBB-NEXT: andi a0, a0, 15
; RV32XTHEADBB-NEXT: add a0, a0, a1
; RV32XTHEADBB-NEXT: ret
;
; RV64XTHEADBB-LABEL: test_ctpop_i16:
Expand All @@ -2388,10 +2387,9 @@ define i16 @test_ctpop_i16(i16 %a) nounwind {
; RV64XTHEADBB-NEXT: add a0, a2, a0
; RV64XTHEADBB-NEXT: srli a1, a0, 4
; RV64XTHEADBB-NEXT: add a0, a0, a1
; RV64XTHEADBB-NEXT: andi a1, a0, 15
; RV64XTHEADBB-NEXT: slli a0, a0, 52
; RV64XTHEADBB-NEXT: srli a0, a0, 60
; RV64XTHEADBB-NEXT: add a0, a1, a0
; RV64XTHEADBB-NEXT: th.extu a1, a0, 11, 8
; RV64XTHEADBB-NEXT: andi a0, a0, 15
; RV64XTHEADBB-NEXT: add a0, a0, a1
; RV64XTHEADBB-NEXT: ret
%1 = call i16 @llvm.ctpop.i16(i16 %a)
ret i16 %1
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16 changes: 16 additions & 0 deletions llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
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Expand Up @@ -702,6 +702,22 @@ define i64 @zext_bf_i64(i64 %a) nounwind {
ret i64 %and
}

define i64 @zext_bf2_i64(i64 %a) nounwind {
; RV64I-LABEL: zext_bf2_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 49
; RV64I-NEXT: ret
;
; RV64XTHEADBB-LABEL: zext_bf2_i64:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: th.extu a0, a0, 15, 1
; RV64XTHEADBB-NEXT: ret
%t0 = and i64 %a, 65535
%result = lshr i64 %t0, 1
ret i64 %result
}

define i64 @zext_i64_srliw(i64 %a) nounwind {
; RV64I-LABEL: zext_i64_srliw:
; RV64I: # %bb.0:
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