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[RISCV] Add scheduling model for Syntacore SCR4 and SCR5 #102909

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Merged
merged 3 commits into from
Aug 14, 2024
Merged

[RISCV] Add scheduling model for Syntacore SCR4 and SCR5 #102909

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2b4cfb3
[NFC] Rename RISCVSchedSyntacoreSCR3.td
asi-sc Aug 12, 2024
251d0d7
[RISCV] Add scheduling model for Syntacore SCR4 and SCR5
asi-sc Jul 5, 2024
2ec6ea5
fixup! [RISCV] Add scheduling model for Syntacore SCR4 and SCR5
asi-sc Aug 13, 2024
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2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCV.td
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Original file line number Diff line number Diff line change
Expand Up @@ -51,7 +51,7 @@ include "RISCVSchedSiFive7.td"
include "RISCVSchedSiFiveP400.td"
include "RISCVSchedSiFiveP600.td"
include "RISCVSchedSyntacoreSCR1.td"
include "RISCVSchedSyntacoreSCR3.td"
include "RISCVSchedSyntacoreSCR345.td"
include "RISCVSchedXiangShanNanHu.td"

//===----------------------------------------------------------------------===//
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8 changes: 4 additions & 4 deletions llvm/lib/Target/RISCV/RISCVProcessors.td
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Expand Up @@ -333,7 +333,7 @@ def SYNTACORE_SCR3_RV64 : RISCVProcessorModel<"syntacore-scr3-rv64",
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;

def SYNTACORE_SCR4_RV32 : RISCVProcessorModel<"syntacore-scr4-rv32",
NoSchedModel,
SyntacoreSCR4RV32Model,
[Feature32Bit,
FeatureStdExtI,
FeatureStdExtZicsr,
Expand All @@ -345,7 +345,7 @@ def SYNTACORE_SCR4_RV32 : RISCVProcessorModel<"syntacore-scr4-rv32",
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;

def SYNTACORE_SCR4_RV64 : RISCVProcessorModel<"syntacore-scr4-rv64",
NoSchedModel,
SyntacoreSCR4RV64Model,
[Feature64Bit,
FeatureStdExtI,
FeatureStdExtZicsr,
Expand All @@ -358,7 +358,7 @@ def SYNTACORE_SCR4_RV64 : RISCVProcessorModel<"syntacore-scr4-rv64",
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;

def SYNTACORE_SCR5_RV32 : RISCVProcessorModel<"syntacore-scr5-rv32",
NoSchedModel,
SyntacoreSCR5RV32Model,
[Feature32Bit,
FeatureStdExtI,
FeatureStdExtZicsr,
Expand All @@ -371,7 +371,7 @@ def SYNTACORE_SCR5_RV32 : RISCVProcessorModel<"syntacore-scr5-rv32",
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;

def SYNTACORE_SCR5_RV64 : RISCVProcessorModel<"syntacore-scr5-rv64",
NoSchedModel,
SyntacoreSCR5RV64Model,
[Feature64Bit,
FeatureStdExtI,
FeatureStdExtZicsr,
Expand Down
189 changes: 0 additions & 189 deletions llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR3.td
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