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[AMDGPU][True16] added Pre-RA hint to improve copy elimination #103366

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Mar 12, 2025
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[AMDGPU][True16] added Pre-RA hint to improve copy elimination #103366

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43 changes: 43 additions & 0 deletions llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -22,12 +22,22 @@
/// although the same shall be possible with other register classes and
/// instructions if necessary.
///
/// This pass also adds register allocation hints to COPY.
/// The hints will be post-processed by SIRegisterInfo::getRegAllocationHints.
/// When using True16, we often see COPY moving a 16-bit value between a VGPR_32
Comment on lines +25 to +27
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These three lines are duplicated below.

/// This pass also adds register allocation hints to COPY.
/// The hints will be post-processed by SIRegisterInfo::getRegAllocationHints.
/// When using True16, we often see COPY moving a 16-bit value between a VGPR_32
/// and a VGPR_16. If we use the VGPR_16 that corresponds to the lo16 bits of
/// the VGPR_32, the COPY can be completely eliminated.
///
//===----------------------------------------------------------------------===//

#include "GCNPreRAOptimizations.h"
#include "AMDGPU.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIRegisterInfo.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/InitializePasses.h"
Expand Down Expand Up @@ -253,5 +263,38 @@ bool GCNPreRAOptimizationsImpl::run(MachineFunction &MF) {
Changed |= processReg(Reg);
}

if (!ST.useRealTrue16Insts())
return Changed;

// Add RA hints to improve True16 COPY elimination.
for (const MachineBasicBlock &MBB : MF) {
for (const MachineInstr &MI : MBB) {
if (MI.getOpcode() != AMDGPU::COPY)
continue;
Register Dst = MI.getOperand(0).getReg();
Register Src = MI.getOperand(1).getReg();
if (Dst.isVirtual() &&
MRI->getRegClass(Dst) == &AMDGPU::VGPR_16RegClass &&
Src.isPhysical() &&
TRI->getRegClassForReg(*MRI, Src) == &AMDGPU::VGPR_32RegClass)
MRI->setRegAllocationHint(Dst, 0, TRI->getSubReg(Src, AMDGPU::lo16));
Comment on lines +276 to +280
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I think this situation should be a hard machine verifier error

if (Src.isVirtual() &&
MRI->getRegClass(Src) == &AMDGPU::VGPR_16RegClass &&
Dst.isPhysical() &&
TRI->getRegClassForReg(*MRI, Dst) == &AMDGPU::VGPR_32RegClass)
MRI->setRegAllocationHint(Src, 0, TRI->getSubReg(Dst, AMDGPU::lo16));
if (!Dst.isVirtual() || !Src.isVirtual())
continue;
if (MRI->getRegClass(Dst) == &AMDGPU::VGPR_32RegClass &&
MRI->getRegClass(Src) == &AMDGPU::VGPR_16RegClass) {
MRI->setRegAllocationHint(Dst, AMDGPURI::Size32, Src);
MRI->setRegAllocationHint(Src, AMDGPURI::Size16, Dst);
}
if (MRI->getRegClass(Dst) == &AMDGPU::VGPR_16RegClass &&
MRI->getRegClass(Src) == &AMDGPU::VGPR_32RegClass)
MRI->setRegAllocationHint(Dst, AMDGPURI::Size16, Src);
}
}

return Changed;
}
67 changes: 67 additions & 0 deletions llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3713,6 +3713,73 @@ const int *SIRegisterInfo::getRegUnitPressureSets(unsigned RegUnit) const {
return AMDGPUGenRegisterInfo::getRegUnitPressureSets(RegUnit);
}

bool SIRegisterInfo::getRegAllocationHints(Register VirtReg,
ArrayRef<MCPhysReg> Order,
SmallVectorImpl<MCPhysReg> &Hints,
const MachineFunction &MF,
const VirtRegMap *VRM,
const LiveRegMatrix *Matrix) const {

const MachineRegisterInfo &MRI = MF.getRegInfo();
const SIRegisterInfo *TRI = ST.getRegisterInfo();

std::pair<unsigned, Register> Hint = MRI.getRegAllocationHint(VirtReg);

switch (Hint.first) {
case AMDGPURI::Size32: {
Register Paired = Hint.second;
assert(Paired);
Register PairedPhys;
if (Paired.isPhysical()) {
PairedPhys =
getMatchingSuperReg(Paired, AMDGPU::lo16, &AMDGPU::VGPR_32RegClass);
} else if (VRM && VRM->hasPhys(Paired)) {
PairedPhys = getMatchingSuperReg(VRM->getPhys(Paired), AMDGPU::lo16,
&AMDGPU::VGPR_32RegClass);
}

// Prefer the paired physreg.
if (PairedPhys)
// isLo(Paired) is implicitly true here from the API of
// getMatchingSuperReg.
Hints.push_back(PairedPhys);
return false;
}
case AMDGPURI::Size16: {
Register Paired = Hint.second;
assert(Paired);
Register PairedPhys;
if (Paired.isPhysical()) {
PairedPhys = TRI->getSubReg(Paired, AMDGPU::lo16);
} else if (VRM && VRM->hasPhys(Paired)) {
PairedPhys = TRI->getSubReg(VRM->getPhys(Paired), AMDGPU::lo16);
}

// First prefer the paired physreg.
if (PairedPhys)
Hints.push_back(PairedPhys);
else {
// Add all the lo16 physregs.
// When the Paired operand has not yet been assigned a physreg it is
// better to try putting VirtReg in a lo16 register, because possibly
// later Paired can be assigned to the overlapping register and the COPY
// can be eliminated.
for (MCPhysReg PhysReg : Order) {
if (PhysReg == PairedPhys || AMDGPU::isHi16Reg(PhysReg, *this))
continue;
if (AMDGPU::VGPR_16RegClass.contains(PhysReg) &&
!MRI.isReserved(PhysReg))
Hints.push_back(PhysReg);
}
}
return false;
}
default:
return TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF,
VRM);
}
}

MCRegister SIRegisterInfo::getReturnAddressReg(const MachineFunction &MF) const {
// Not a callee saved register.
return AMDGPU::SGPR30_SGPR31;
Expand Down
12 changes: 12 additions & 0 deletions llvm/lib/Target/AMDGPU/SIRegisterInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -29,6 +29,13 @@ class LiveRegUnits;
class RegisterBank;
struct SGPRSpillBuilder;

/// Register allocation hint types. Helps eliminate unneeded COPY with True16
namespace AMDGPURI {

enum { Size16 = 1, Size32 = 2 };

} // end namespace AMDGPURI

class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
private:
const GCNSubtarget &ST;
Expand Down Expand Up @@ -329,6 +336,11 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
unsigned getRegPressureSetLimit(const MachineFunction &MF,
unsigned Idx) const override;

bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
SmallVectorImpl<MCPhysReg> &Hints,
const MachineFunction &MF, const VirtRegMap *VRM,
const LiveRegMatrix *Matrix) const override;

const int *getRegUnitPressureSets(unsigned RegUnit) const override;

MCRegister getReturnAddressReg(const MachineFunction &MF) const;
Expand Down
91 changes: 41 additions & 50 deletions llvm/test/CodeGen/AMDGPU/bf16.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -37712,12 +37712,10 @@ define bfloat @v_select_bf16(i1 %cond, bfloat %a, bfloat %b) {
; GFX11TRUE16-LABEL: v_select_bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 1, v0
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_select_bf16:
Expand Down Expand Up @@ -37785,14 +37783,11 @@ define bfloat @v_select_fneg_lhs_bf16(i1 %cond, bfloat %a, bfloat %b) {
; GFX11TRUE16-LABEL: v_select_fneg_lhs_bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 1, v0
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
; GFX11TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v0.h, v0.l, vcc_lo
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v1.l
; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_select_fneg_lhs_bf16:
Expand Down Expand Up @@ -37862,14 +37857,11 @@ define bfloat @v_select_fneg_rhs_bf16(i1 %cond, bfloat %a, bfloat %b) {
; GFX11TRUE16-LABEL: v_select_fneg_rhs_bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 1, v0
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
; GFX11TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v2.l
; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, vcc_lo
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_select_fneg_rhs_bf16:
Expand Down Expand Up @@ -42659,17 +42651,16 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX11TRUE16-NEXT: scratch_load_b32 v85, off, s32 offset:72
; GFX11TRUE16-NEXT: scratch_load_b32 v86, off, s32 offset:4
; GFX11TRUE16-NEXT: scratch_load_b32 v87, off, s32 offset:68
; GFX11TRUE16-NEXT: v_and_b32_e32 v16, 1, v16
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v14, 1, v14
; GFX11TRUE16-NEXT: v_and_b32_e32 v16, 1, v16
; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 1, v18
; GFX11TRUE16-NEXT: v_and_b32_e32 v20, 1, v20
; GFX11TRUE16-NEXT: v_and_b32_e32 v22, 1, v22
; GFX11TRUE16-NEXT: v_and_b32_e32 v24, 1, v24
; GFX11TRUE16-NEXT: v_and_b32_e32 v26, 1, v26
; GFX11TRUE16-NEXT: v_and_b32_e32 v28, 1, v28
; GFX11TRUE16-NEXT: v_and_b32_e32 v30, 1, v30
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s15, 1, v16
; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 1, v1
; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 1, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 1, v3
Expand All @@ -42693,6 +42684,7 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX11TRUE16-NEXT: v_and_b32_e32 v29, 1, v29
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s13, 1, v14
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s15, 1, v16
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s17, 1, v18
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s19, 1, v20
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s21, 1, v22
Expand Down Expand Up @@ -42722,45 +42714,44 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s26, 1, v27
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s29, 1, v29
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(32)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v16.l, v31.l
; GFX11TRUE16-NEXT: v_and_b32_e32 v31, 1, v31
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(31)
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v32
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v32
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(30)
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v33
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v33
; GFX11TRUE16-NEXT: v_cndmask_b16 v15.l, v33.l, v32.l, s28
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(29)
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v34
; GFX11TRUE16-NEXT: v_and_b32_e32 v16, 1, v16
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v34
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(28)
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v35
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v35
; GFX11TRUE16-NEXT: v_cndmask_b16 v14.l, v35.l, v34.l, s27
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(27)
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v36
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v36
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(26)
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v37
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v37
; GFX11TRUE16-NEXT: v_cndmask_b16 v13.l, v37.l, v36.l, s25
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(25)
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v38
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v38
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(24)
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v39
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v39
; GFX11TRUE16-NEXT: v_cndmask_b16 v12.l, v39.l, v38.l, s23
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(23)
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v48
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v48
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(22)
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v49
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v49
; GFX11TRUE16-NEXT: v_cndmask_b16 v11.l, v49.l, v48.l, s21
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(21)
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v50
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v50
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(20)
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v51
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v51
; GFX11TRUE16-NEXT: v_cndmask_b16 v10.l, v51.l, v50.l, s19
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(19)
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v52
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v52
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(18)
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v53
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v53
; GFX11TRUE16-NEXT: v_cndmask_b16 v9.l, v53.l, v52.l, s17
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(17)
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v54
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v54
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(16)
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v55
; GFX11TRUE16-NEXT: v_cndmask_b16 v8.l, v55.l, v54.l, s15
Expand Down Expand Up @@ -42798,20 +42789,20 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v87
; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v87.l, v86.l, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v31
; GFX11TRUE16-NEXT: v_cndmask_b16 v6.l, v67.l, v66.l, s11
; GFX11TRUE16-NEXT: v_cndmask_b16 v5.l, v69.l, v68.l, s9
; GFX11TRUE16-NEXT: v_cndmask_b16 v4.l, v71.l, v70.l, s7
; GFX11TRUE16-NEXT: v_cndmask_b16 v3.l, v81.l, v80.l, s5
; GFX11TRUE16-NEXT: v_cndmask_b16 v2.l, v83.l, v82.l, s3
; GFX11TRUE16-NEXT: v_cndmask_b16 v1.l, v85.l, v84.l, s1
; GFX11TRUE16-NEXT: v_cndmask_b16 v14.h, v20.l, v19.l, s29
; GFX11TRUE16-NEXT: v_cndmask_b16 v13.h, v22.l, v21.l, s26
; GFX11TRUE16-NEXT: v_cndmask_b16 v12.h, v24.l, v23.l, s24
; GFX11TRUE16-NEXT: v_cndmask_b16 v11.h, v26.l, v25.l, s22
; GFX11TRUE16-NEXT: v_cndmask_b16 v10.h, v28.l, v27.l, s20
; GFX11TRUE16-NEXT: v_cndmask_b16 v9.h, v30.l, v29.l, s18
; GFX11TRUE16-NEXT: v_cndmask_b16 v8.h, v32.l, v31.l, s16
; GFX11TRUE16-NEXT: v_cndmask_b16 v14.h, v19.l, v18.l, s29
; GFX11TRUE16-NEXT: v_cndmask_b16 v13.h, v21.l, v20.l, s26
; GFX11TRUE16-NEXT: v_cndmask_b16 v12.h, v23.l, v22.l, s24
; GFX11TRUE16-NEXT: v_cndmask_b16 v11.h, v25.l, v24.l, s22
; GFX11TRUE16-NEXT: v_cndmask_b16 v10.h, v27.l, v26.l, s20
; GFX11TRUE16-NEXT: v_cndmask_b16 v9.h, v29.l, v28.l, s18
; GFX11TRUE16-NEXT: v_cndmask_b16 v8.h, v32.l, v30.l, s16
; GFX11TRUE16-NEXT: v_cndmask_b16 v7.h, v34.l, v33.l, s14
; GFX11TRUE16-NEXT: v_cndmask_b16 v6.h, v36.l, v35.l, s12
; GFX11TRUE16-NEXT: v_cndmask_b16 v5.h, v38.l, v37.l, s10
Expand All @@ -42820,7 +42811,7 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX11TRUE16-NEXT: v_cndmask_b16 v1.h, v54.l, v53.l, s2
; GFX11TRUE16-NEXT: v_cndmask_b16 v2.h, v52.l, v51.l, s4
; GFX11TRUE16-NEXT: v_cndmask_b16 v3.h, v50.l, v49.l, s6
; GFX11TRUE16-NEXT: v_cndmask_b16 v15.h, v18.l, v17.l, vcc_lo
; GFX11TRUE16-NEXT: v_cndmask_b16 v15.h, v17.l, v16.l, vcc_lo
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_vselect_v32bf16:
Expand Down
8 changes: 3 additions & 5 deletions llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
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Expand Up @@ -908,10 +908,9 @@ define <2 x i16> @chain_hi_to_lo_global_other_dep(ptr addrspace(1) %ptr) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: global_load_d16_hi_b16 v0, v[0:1], off glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 12 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v1, v0
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v2, v0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: chain_hi_to_lo_global_other_dep:
Expand Down Expand Up @@ -981,12 +980,11 @@ define <2 x i16> @chain_hi_to_lo_flat_other_dep(ptr addrspace(0) %ptr) {
; GFX11-TRUE16-NEXT: flat_load_d16_b16 v2, v[0:1] offset:2 glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: flat_load_d16_hi_b16 v0, v[0:1] glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(1)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 12 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v1, v0
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v2, v0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: chain_hi_to_lo_flat_other_dep:
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8 changes: 2 additions & 6 deletions llvm/test/CodeGen/AMDGPU/fadd.f16.ll
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Expand Up @@ -76,9 +76,7 @@ define amdgpu_kernel void @fadd_f16(
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX11-SDAG-NEXT: buffer_load_u16 v1, off, s[4:7], 0 glc dlc
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX11-SDAG-NEXT: v_mov_b16_e32 v0.h, v1.l
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
; GFX11-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
; GFX11-SDAG-NEXT: buffer_store_b16 v0, off, s[8:11], 0
; GFX11-SDAG-NEXT: s_endpgm
;
Expand All @@ -98,9 +96,7 @@ define amdgpu_kernel void @fadd_f16(
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX11-GISEL-NEXT: buffer_load_u16 v1, off, s[4:7], 0 glc dlc
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX11-GISEL-NEXT: v_mov_b16_e32 v0.h, v1.l
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
; GFX11-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
; GFX11-GISEL-NEXT: buffer_store_b16 v0, off, s[0:3], 0
; GFX11-GISEL-NEXT: s_endpgm
;
Expand Down
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