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merged 2 commits into from
Aug 21, 2024
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RISC-V: Add fminimumnum and fmaximumnum support #104411

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c5d6e33
RISC-V: Add fminimumnum and fmaximumnum support
wzssyqa Aug 15, 2024
6ac56df
split fp-maximumnum-minimumnum.ll
wzssyqa Aug 20, 2024
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36 changes: 21 additions & 15 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -365,12 +365,13 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SELECT, XLenVT, Custom);

static const unsigned FPLegalNodeTypes[] = {
ISD::FMINNUM, ISD::FMAXNUM, ISD::LRINT,
ISD::LLRINT, ISD::LROUND, ISD::LLROUND,
ISD::STRICT_LRINT, ISD::STRICT_LLRINT, ISD::STRICT_LROUND,
ISD::STRICT_LLROUND, ISD::STRICT_FMA, ISD::STRICT_FADD,
ISD::STRICT_FSUB, ISD::STRICT_FMUL, ISD::STRICT_FDIV,
ISD::STRICT_FSQRT, ISD::STRICT_FSETCC, ISD::STRICT_FSETCCS};
ISD::FMINNUM, ISD::FMAXNUM, ISD::FMINIMUMNUM,
ISD::FMAXIMUMNUM, ISD::LRINT, ISD::LLRINT,
ISD::LROUND, ISD::LLROUND, ISD::STRICT_LRINT,
ISD::STRICT_LLRINT, ISD::STRICT_LROUND, ISD::STRICT_LLROUND,
ISD::STRICT_FMA, ISD::STRICT_FADD, ISD::STRICT_FSUB,
ISD::STRICT_FMUL, ISD::STRICT_FDIV, ISD::STRICT_FSQRT,
ISD::STRICT_FSETCC, ISD::STRICT_FSETCCS};

static const ISD::CondCode FPCCToExpand[] = {
ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT,
Expand All @@ -389,15 +390,20 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::BITCAST, MVT::i16, Custom);

static const unsigned ZfhminZfbfminPromoteOps[] = {
ISD::FMINNUM, ISD::FMAXNUM, ISD::FADD,
ISD::FSUB, ISD::FMUL, ISD::FMA,
ISD::FDIV, ISD::FSQRT, ISD::FABS,
ISD::FNEG, ISD::STRICT_FMA, ISD::STRICT_FADD,
ISD::STRICT_FSUB, ISD::STRICT_FMUL, ISD::STRICT_FDIV,
ISD::STRICT_FSQRT, ISD::STRICT_FSETCC, ISD::STRICT_FSETCCS,
ISD::SETCC, ISD::FCEIL, ISD::FFLOOR,
ISD::FTRUNC, ISD::FRINT, ISD::FROUND,
ISD::FROUNDEVEN, ISD::SELECT};
ISD::FMINNUM, ISD::FMAXNUM,
ISD::FMAXIMUMNUM, ISD::FMINIMUMNUM,
ISD::FADD, ISD::FSUB,
ISD::FMUL, ISD::FMA,
ISD::FDIV, ISD::FSQRT,
ISD::FABS, ISD::FNEG,
ISD::STRICT_FMA, ISD::STRICT_FADD,
ISD::STRICT_FSUB, ISD::STRICT_FMUL,
ISD::STRICT_FDIV, ISD::STRICT_FSQRT,
ISD::STRICT_FSETCC, ISD::STRICT_FSETCCS,
ISD::SETCC, ISD::FCEIL,
ISD::FFLOOR, ISD::FTRUNC,
ISD::FRINT, ISD::FROUND,
ISD::FROUNDEVEN, ISD::SELECT};

if (Subtarget.hasStdExtZfbfmin()) {
setOperationAction(ISD::BITCAST, MVT::i16, Custom);
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2 changes: 2 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfoD.td
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Expand Up @@ -392,6 +392,8 @@ def : Pat<(fneg (any_fma_nsz FPR64IN32X:$rs1, FPR64IN32X:$rs2, FPR64IN32X:$rs3))
foreach Ext = DExts in {
defm : PatFprFpr_m<fminnum, FMIN_D, Ext>;
defm : PatFprFpr_m<fmaxnum, FMAX_D, Ext>;
defm : PatFprFpr_m<fminimumnum, FMIN_D, Ext>;
defm : PatFprFpr_m<fmaximumnum, FMAX_D, Ext>;
defm : PatFprFpr_m<riscv_fmin, FMIN_D, Ext>;
defm : PatFprFpr_m<riscv_fmax, FMAX_D, Ext>;
}
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2 changes: 2 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfoF.td
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Expand Up @@ -603,6 +603,8 @@ def : Pat<(fneg (any_fma_nsz FPR32INX:$rs1, FPR32INX:$rs2, FPR32INX:$rs3)),
foreach Ext = FExts in {
defm : PatFprFpr_m<fminnum, FMIN_S, Ext>;
defm : PatFprFpr_m<fmaxnum, FMAX_S, Ext>;
defm : PatFprFpr_m<fminimumnum, FMIN_S, Ext>;
defm : PatFprFpr_m<fmaximumnum, FMAX_S, Ext>;
defm : PatFprFpr_m<riscv_fmin, FMIN_S, Ext>;
defm : PatFprFpr_m<riscv_fmax, FMAX_S, Ext>;
}
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2 changes: 2 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
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Original file line number Diff line number Diff line change
Expand Up @@ -347,6 +347,8 @@ def : Pat<(fneg (any_fma_nsz FPR16INX:$rs1, FPR16INX:$rs2, FPR16INX:$rs3)),
foreach Ext = ZfhExts in {
defm : PatFprFpr_m<fminnum, FMIN_H, Ext>;
defm : PatFprFpr_m<fmaxnum, FMAX_H, Ext>;
defm : PatFprFpr_m<fminimumnum, FMIN_H, Ext>;
defm : PatFprFpr_m<fmaximumnum, FMAX_H, Ext>;
defm : PatFprFpr_m<riscv_fmin, FMIN_H, Ext>;
defm : PatFprFpr_m<riscv_fmax, FMAX_H, Ext>;
}
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86 changes: 86 additions & 0 deletions llvm/test/CodeGen/RISCV/double-intrinsics.ll
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Expand Up @@ -1545,3 +1545,89 @@ define i1 @isnan_d_fpclass(double %x) {
%1 = call i1 @llvm.is.fpclass.f64(double %x, i32 3) ; nan
ret i1 %1
}

declare double @llvm.maximumnum.f64(double, double)

define double @maximumnum_double(double %x, double %y) {
; CHECKIFD-LABEL: maximumnum_double:
; CHECKIFD: # %bb.0:
; CHECKIFD-NEXT: fmax.d fa0, fa0, fa1
; CHECKIFD-NEXT: ret
;
; RV32IZFINXZDINX-LABEL: maximumnum_double:
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a2
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: maximumnum_double:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, a1
; RV64IZFINXZDINX-NEXT: ret
;
; RV32I-LABEL: maximumnum_double:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: call fmaximum_num
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: maximumnum_double:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: call fmaximum_num
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%z = call double @llvm.maximumnum.f64(double %x, double %y)
ret double %z
}

declare double @llvm.minimumnum.f64(double, double)

define double @minimumnum_double(double %x, double %y) {
; CHECKIFD-LABEL: minimumnum_double:
; CHECKIFD: # %bb.0:
; CHECKIFD-NEXT: fmin.d fa0, fa0, fa1
; CHECKIFD-NEXT: ret
;
; RV32IZFINXZDINX-LABEL: minimumnum_double:
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: minimumnum_double:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a1
; RV64IZFINXZDINX-NEXT: ret
;
; RV32I-LABEL: minimumnum_double:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: call fminimum_num
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: minimumnum_double:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: call fminimum_num
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%z = call double @llvm.minimumnum.f64(double %x, double %y)
ret double %z
}
96 changes: 96 additions & 0 deletions llvm/test/CodeGen/RISCV/float-intrinsics.ll
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Expand Up @@ -2185,3 +2185,99 @@ define i1 @isnotfinite_fpclass(float %x) {
%1 = call i1 @llvm.is.fpclass.f32(float %x, i32 519) ; ox207 = "inf|nan"
ret i1 %1
}

declare float @llvm.maximumnum.f32(float, float)

define float @maximumnum_float(float %x, float %y) {
; RV32IF-LABEL: maximumnum_float:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fmax.s fa0, fa0, fa1
; RV32IF-NEXT: ret
;
; RV32IZFINX-LABEL: maximumnum_float:
; RV32IZFINX: # %bb.0:
; RV32IZFINX-NEXT: fmax.s a0, a0, a1
; RV32IZFINX-NEXT: ret
;
; RV64IF-LABEL: maximumnum_float:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fmax.s fa0, fa0, fa1
; RV64IF-NEXT: ret
;
; RV64IZFINX-LABEL: maximumnum_float:
; RV64IZFINX: # %bb.0:
; RV64IZFINX-NEXT: fmax.s a0, a0, a1
; RV64IZFINX-NEXT: ret
;
; RV32I-LABEL: maximumnum_float:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: call fmaximum_numf
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: maximumnum_float:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: call fmaximum_numf
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%z = call float @llvm.maximumnum.f32(float %x, float %y)
ret float %z
}

declare float @llvm.minimumnum.f32(float, float)

define float @minimumnum_float(float %x, float %y) {
; RV32IF-LABEL: minimumnum_float:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fmin.s fa0, fa0, fa1
; RV32IF-NEXT: ret
;
; RV32IZFINX-LABEL: minimumnum_float:
; RV32IZFINX: # %bb.0:
; RV32IZFINX-NEXT: fmin.s a0, a0, a1
; RV32IZFINX-NEXT: ret
;
; RV64IF-LABEL: minimumnum_float:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fmin.s fa0, fa0, fa1
; RV64IF-NEXT: ret
;
; RV64IZFINX-LABEL: minimumnum_float:
; RV64IZFINX: # %bb.0:
; RV64IZFINX-NEXT: fmin.s a0, a0, a1
; RV64IZFINX-NEXT: ret
;
; RV32I-LABEL: minimumnum_float:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: call fminimum_numf
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: minimumnum_float:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: call fminimum_numf
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%z = call float @llvm.minimumnum.f32(float %x, float %y)
ret float %z
}
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