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[SelectionDAG][X86] Add SelectionDAG::getSignedConstant and use it in a few places. #104555

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Merged
merged 2 commits into from
Aug 16, 2024
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[SelectionDAG][X86] Add SelectionDAG::getSignedConstant and use it in a few places. #104555

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[SelectionDAG][X86] Add SelectionDAG::getSignedConstant and use it in…
topperc Aug 16, 2024
5cb2680
fixup! Add = to comment.
topperc Aug 16, 2024
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3 changes: 3 additions & 0 deletions llvm/include/llvm/CodeGen/SelectionDAG.h
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Original file line number Diff line number Diff line change
Expand Up @@ -672,6 +672,9 @@ class SelectionDAG {
SDValue getConstant(const APInt &Val, const SDLoc &DL, EVT VT,
bool isTarget = false, bool isOpaque = false);

SDValue getSignedConstant(int64_t Val, const SDLoc &DL, EVT VT,
bool isTarget = false, bool isOpaque = false);

SDValue getAllOnesConstant(const SDLoc &DL, EVT VT, bool IsTarget = false,
bool IsOpaque = false);

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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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Expand Up @@ -2601,7 +2601,7 @@ SDValue SelectionDAGLegalize::expandFrexp(SDNode *Node) const {
SDValue IsDenormal =
DAG.getSetCC(dl, SetCCVT, Abs, SmallestNormalizedInt, ISD::SETULT);

SDValue MinExp = DAG.getConstant(MinExpVal, dl, ExpVT);
SDValue MinExp = DAG.getSignedConstant(MinExpVal, dl, ExpVT);
SDValue Zero = DAG.getConstant(0, dl, ExpVT);

SDValue ScaledAsInt = DAG.getNode(ISD::BITCAST, dl, AsIntVT, ScaleUp);
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9 changes: 9 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Expand Up @@ -1747,6 +1747,15 @@ SDValue SelectionDAG::getConstant(const ConstantInt &Val, const SDLoc &DL,
return Result;
}

SDValue SelectionDAG::getSignedConstant(int64_t Val, const SDLoc &DL, EVT VT,
bool isT, bool isO) {
unsigned Size = VT.getScalarSizeInBits();
assert(
isIntN(Size, Val) &&
"getSignedConstant with a int64_t value that doesn't fit in the type!");
return getConstant(APInt(Size, Val, true), DL, VT, isT, isO);
}

SDValue SelectionDAG::getAllOnesConstant(const SDLoc &DL, EVT VT, bool IsTarget,
bool IsOpaque) {
return getConstant(APInt::getAllOnes(VT.getScalarSizeInBits()), DL, VT,
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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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Expand Up @@ -4474,7 +4474,7 @@ void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {

// Mask out the low bits for alignment purposes.
AllocSize = DAG.getNode(ISD::AND, dl, AllocSize.getValueType(), AllocSize,
DAG.getConstant(~StackAlignMask, dl, IntPtr));
DAG.getSignedConstant(~StackAlignMask, dl, IntPtr));

SDValue Ops[] = {
getRoot(), AllocSize,
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4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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Expand Up @@ -6349,9 +6349,9 @@ SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
}

MagicFactors.push_back(DAG.getConstant(magics.Magic, dl, SVT));
Factors.push_back(DAG.getConstant(NumeratorFactor, dl, SVT));
Factors.push_back(DAG.getSignedConstant(NumeratorFactor, dl, SVT));
Shifts.push_back(DAG.getConstant(magics.ShiftAmount, dl, ShSVT));
ShiftMasks.push_back(DAG.getConstant(ShiftMask, dl, SVT));
ShiftMasks.push_back(DAG.getSignedConstant(ShiftMask, dl, SVT));
return true;
};

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10 changes: 6 additions & 4 deletions llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
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Expand Up @@ -314,7 +314,8 @@ namespace {
Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, AM.Disp,
AM.SymbolFlags);
else
Disp = CurDAG->getTargetConstant(AM.Disp, DL, MVT::i32);
Disp =
CurDAG->getSignedConstant(AM.Disp, DL, MVT::i32, /*isTarget=*/true);

if (AM.Segment.getNode())
Segment = AM.Segment;
Expand Down Expand Up @@ -2130,7 +2131,7 @@ static bool foldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N,
X = NewX;
}

SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, DL, VT);
SDValue NewMask = DAG.getSignedConstant(Mask >> ShiftAmt, DL, VT);
SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);
SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));

Expand Down Expand Up @@ -3733,7 +3734,8 @@ bool X86DAGToDAGISel::foldLoadStoreIntoMemOperand(SDNode *Node) {
}

if (MemVT != MVT::i64 || isInt<32>(OperandV)) {
Operand = CurDAG->getTargetConstant(OperandV, SDLoc(Node), MemVT);
Operand = CurDAG->getSignedConstant(OperandV, SDLoc(Node), MemVT,
/*isTarget=*/true);
NewOpc = SelectImmOpcode(Opc);
}
}
Expand Down Expand Up @@ -4507,7 +4509,7 @@ bool X86DAGToDAGISel::tryShrinkShlLogicImm(SDNode *N) {
X = NewX;
}

SDValue NewCst = CurDAG->getConstant(ShiftedVal, dl, NVT);
SDValue NewCst = CurDAG->getSignedConstant(ShiftedVal, dl, NVT);
insertDAGNode(*CurDAG, SDValue(N, 0), NewCst);
SDValue NewBinOp = CurDAG->getNode(Opcode, dl, NVT, X, NewCst);
insertDAGNode(*CurDAG, SDValue(N, 0), NewBinOp);
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19 changes: 10 additions & 9 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Expand Up @@ -10763,9 +10763,9 @@ static SDValue lowerShuffleAsBlend(const SDLoc &DL, MVT VT, SDValue V1,
for (int i = 0, Size = Mask.size(); i < Size; ++i)
for (int j = 0; j < Scale; ++j)
VSELECTMask.push_back(
Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
: DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
MVT::i8));
Mask[i] < 0
? DAG.getUNDEF(MVT::i8)
: DAG.getSignedConstant(Mask[i] < Size ? -1 : 0, DL, MVT::i8));

V1 = DAG.getBitcast(BlendVT, V1);
V2 = DAG.getBitcast(BlendVT, V2);
Expand Down Expand Up @@ -18650,7 +18650,7 @@ SDValue X86TargetLowering::LowerGlobalOrExternal(SDValue Op, SelectionDAG &DAG,
// addition for it.
if (Offset != 0)
Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
DAG.getConstant(Offset, dl, PtrVT));
DAG.getSignedConstant(Offset, dl, PtrVT));

return Result;
}
Expand Down Expand Up @@ -24971,9 +24971,9 @@ X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
Result = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
}
if (Alignment && *Alignment > StackAlign)
Result =
DAG.getNode(ISD::AND, dl, VT, Result,
DAG.getConstant(~(Alignment->value() - 1ULL), dl, VT));
Result = DAG.getNode(
ISD::AND, dl, VT, Result,
DAG.getSignedConstant(~(Alignment->value() - 1ULL), dl, VT));
Chain = DAG.getCopyToReg(Chain, dl, SPReg, Result); // Output chain
} else if (SplitStack) {
MachineRegisterInfo &MRI = MF.getRegInfo();
Expand Down Expand Up @@ -25005,8 +25005,9 @@ X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
Chain = SP.getValue(1);

if (Alignment) {
SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
DAG.getConstant(~(Alignment->value() - 1ULL), dl, VT));
SP = DAG.getNode(
ISD::AND, dl, VT, SP.getValue(0),
DAG.getSignedConstant(~(Alignment->value() - 1ULL), dl, VT));
Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
}

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