Skip to content

[RISCV] Decompose LMUL > 1 reverses into LMUL * M1 vrgather.vv #104574

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 6 commits into from
Aug 29, 2024
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
47 changes: 44 additions & 3 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -10328,6 +10328,50 @@ SDValue RISCVTargetLowering::lowerVECTOR_REVERSE(SDValue Op,
Vec = convertToScalableVector(ContainerVT, Vec, DAG, Subtarget);
}

MVT XLenVT = Subtarget.getXLenVT();
auto [Mask, VL] = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget);

// On some uarchs vrgather.vv will read from every input register for each
// output register, regardless of the indices. However to reverse a vector
// each output register only needs to read from one register. So decompose it
// into LMUL * M1 vrgather.vvs, so we get O(LMUL) performance instead of
// O(LMUL^2).
//
// vsetvli a1, zero, e64, m4, ta, ma
// vrgatherei16.vv v12, v8, v16
// ->
// vsetvli a1, zero, e64, m1, ta, ma
// vrgather.vv v15, v8, v16
// vrgather.vv v14, v9, v16
// vrgather.vv v13, v10, v16
// vrgather.vv v12, v11, v16
if (ContainerVT.bitsGT(getLMUL1VT(ContainerVT)) &&
ContainerVT.getVectorElementCount().isKnownMultipleOf(2)) {
auto [Lo, Hi] = DAG.SplitVector(Vec, DL);
Lo = DAG.getNode(ISD::VECTOR_REVERSE, DL, Lo.getSimpleValueType(), Lo);
Hi = DAG.getNode(ISD::VECTOR_REVERSE, DL, Hi.getSimpleValueType(), Hi);
SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, DL, ContainerVT, Hi, Lo);

// Fixed length vectors might not fit exactly into their container, and so
// leave a gap in the front of the vector after being reversed. Slide this
// away.
//
// x x x x 3 2 1 0 <- v4i16 @ vlen=128
// 0 1 2 3 x x x x <- reverse
// x x x x 0 1 2 3 <- vslidedown.vx
if (VecVT.isFixedLengthVector()) {
SDValue Offset = DAG.getNode(
ISD::SUB, DL, XLenVT,
DAG.getElementCount(DL, XLenVT, ContainerVT.getVectorElementCount()),
DAG.getElementCount(DL, XLenVT, VecVT.getVectorElementCount()));
Concat =
getVSlidedown(DAG, Subtarget, DL, ContainerVT,
DAG.getUNDEF(ContainerVT), Concat, Offset, Mask, VL);
Concat = convertFromScalableVector(VecVT, Concat, DAG, Subtarget);
}
return Concat;
}

unsigned EltSize = ContainerVT.getScalarSizeInBits();
unsigned MinSize = ContainerVT.getSizeInBits().getKnownMinValue();
unsigned VectorBitsMax = Subtarget.getRealMaxVLen();
Expand Down Expand Up @@ -10375,9 +10419,6 @@ SDValue RISCVTargetLowering::lowerVECTOR_REVERSE(SDValue Op,
IntVT = IntVT.changeVectorElementType(MVT::i16);
}

MVT XLenVT = Subtarget.getXLenVT();
auto [Mask, VL] = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget);

// Calculate VLMAX-1 for the desired SEW.
SDValue VLMinus1 = DAG.getNode(
ISD::SUB, DL, XLenVT,
Expand Down
Loading
Loading