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[LLVM][AArch64] Fix invalid use of AArch64ISD::UZP2 in performConcatVectorsCombine. #104774

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Merged
merged 1 commit into from
Aug 30, 2024
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[LLVM][AArch64] Fix invalid use of AArch64ISD::UZP2 in performConcatVectorsCombine. #104774

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14 changes: 9 additions & 5 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -19811,15 +19811,15 @@ static SDValue performConcatVectorsCombine(SDNode *N,
// This optimization reduces instruction count.
if (N00Opc == AArch64ISD::VLSHR && N10Opc == AArch64ISD::VLSHR &&
N00->getOperand(1) == N10->getOperand(1)) {

SDValue N000 = N00->getOperand(0);
SDValue N100 = N10->getOperand(0);
uint64_t N001ConstVal = N00->getConstantOperandVal(1),
N101ConstVal = N10->getConstantOperandVal(1),
NScalarSize = N->getValueType(0).getScalarSizeInBits();

if (N001ConstVal == N101ConstVal && N001ConstVal > NScalarSize) {

N000 = DAG.getNode(AArch64ISD::NVCAST, dl, VT, N000);
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Would it be possible to test this fix?

I think a comment is warranted at least. I take it this has something to do with big-endian mode?

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By enabling the verification within verifyTargetSDNode for fixed-length vectors the code is tested (i.e. if you remove this code make check will assert.

N100 = DAG.getNode(AArch64ISD::NVCAST, dl, VT, N100);
SDValue Uzp = DAG.getNode(AArch64ISD::UZP2, dl, VT, N000, N100);
SDValue NewShiftConstant =
DAG.getConstant(N001ConstVal - NScalarSize, dl, MVT::i32);
Expand Down Expand Up @@ -29264,8 +29264,10 @@ void AArch64TargetLowering::verifyTargetSDNode(const SDNode *N) const {
assert(OpVT.getSizeInBits() == VT.getSizeInBits() &&
"Expected vectors of equal size!");
// TODO: Enable assert once bogus creations have been fixed.
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Can this TODO be removed now that the assert has been uncommented?

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The assert is still disabled for scalable vectors.

// assert(OpVT.getVectorElementCount() == VT.getVectorElementCount()*2 &&
// "Expected result vector with half the lanes of its input!");
if (VT.isScalableVector())
break;
assert(OpVT.getVectorElementCount() == VT.getVectorElementCount() * 2 &&
"Expected result vector with half the lanes of its input!");
break;
}
case AArch64ISD::TRN1:
Expand All @@ -29282,7 +29284,9 @@ void AArch64TargetLowering::verifyTargetSDNode(const SDNode *N) const {
assert(VT.isVector() && Op0VT.isVector() && Op1VT.isVector() &&
"Expected vectors!");
// TODO: Enable assert once bogus creations have been fixed.
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Ditto for this TODO comment.

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As above.

// assert(VT == Op0VT && VT == Op1VT && "Expected matching vectors!");
if (VT.isScalableVector())
break;
assert(VT == Op0VT && VT == Op1VT && "Expected matching vectors!");
break;
}
}
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