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[RISCV] Remove experimental for Ssqosid ext #105476

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2 changes: 1 addition & 1 deletion clang/test/Driver/print-supported-extensions-riscv.c
Original file line number Diff line number Diff line change
Expand Up @@ -126,6 +126,7 @@
// CHECK-NEXT: sscofpmf 1.0 'Sscofpmf' (Count Overflow and Mode-Based Filtering)
// CHECK-NEXT: sscounterenw 1.0 'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero)
// CHECK-NEXT: sscsrind 1.0 'Sscsrind' (Indirect CSR Access Supervisor Level)
// CHECK-NEXT: ssqosid 1.0 'Ssqosid' (Quality-of-Service (QoS) Identifiers)
// CHECK-NEXT: ssstateen 1.0 'Ssstateen' (Supervisor-mode view of the state-enable extension)
// CHECK-NEXT: ssstrict 1.0 'Ssstrict' (No non-conforming extensions are present)
// CHECK-NEXT: sstc 1.0 'Sstc' (Supervisor-mode timer interrupts)
Expand Down Expand Up @@ -178,7 +179,6 @@
// CHECK-NEXT: smnpm 1.0 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)
// CHECK-NEXT: ssnpm 1.0 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)
// CHECK-NEXT: sspm 1.0 'Sspm' (Indicates Supervisor-mode Pointer Masking)
// CHECK-NEXT: ssqosid 1.0 'Ssqosid' (Quality-of-Service (QoS) Identifiers)
// CHECK-NEXT: supm 1.0 'Supm' (Indicates User-mode Pointer Masking)
// CHECK-EMPTY:
// CHECK-NEXT: Supported Profiles
Expand Down
18 changes: 9 additions & 9 deletions clang/test/Preprocessor/riscv-target-features.c
Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,7 @@
// CHECK-NOT: __riscv_sscofpmf {{.*$}}
// CHECK-NOT: __riscv_sscounterenw {{.*$}}
// CHECK-NOT: __riscv_sscsrind {{.*$}}
// CHECK-NOT: __riscv_ssqosid{{.*$}}
// CHECK-NOT: __riscv_ssstateen {{.*$}}
// CHECK-NOT: __riscv_ssstrict {{.*$}}
// CHECK-NOT: __riscv_sstc {{.*$}}
Expand Down Expand Up @@ -179,7 +180,6 @@
// CHECK-NOT: __riscv_smnpm{{.*$}}
// CHECK-NOT: __riscv_ssnpm{{.*$}}
// CHECK-NOT: __riscv_sspm{{.*$}}
// CHECK-NOT: __riscv_ssqosid{{.*$}}
// CHECK-NOT: __riscv_supm{{.*$}}
// CHECK-NOT: __riscv_zacas {{.*$}}
// CHECK-NOT: __riscv_zalasr {{.*$}}
Expand Down Expand Up @@ -1415,6 +1415,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SSCSRIND-EXT %s
// CHECK-SSCSRIND-EXT: __riscv_sscsrind 1000000{{$}}

// RUN: %clang --target=riscv32 \
// RUN: -march=rv32i_ssqosid1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s
// RUN: %clang --target=riscv64 \
// RUN: -march=rv64i_ssqosid1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s
// CHECK-SSQOSID-EXT: __riscv_ssqosid 1000000{{$}}

// RUN: %clang --target=riscv32 \
// RUN: -march=rv32ismcdeleg1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMCDELEG-EXT %s
Expand Down Expand Up @@ -1740,14 +1748,6 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
// CHECK-SUPM-EXT: __riscv_supm 1000000{{$}}

// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_ssqosid1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
// RUN: -march=rv64i_ssqosid1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s
// CHECK-SSQOSID-EXT: __riscv_ssqosid 1000000{{$}}

// Misaligned

// RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i -E -dM %s \
Expand Down
4 changes: 1 addition & 3 deletions llvm/docs/RISCVUsage.rst
Original file line number Diff line number Diff line change
Expand Up @@ -136,6 +136,7 @@ on support follow.
``Sscofpmf`` Assembly Support
``Sscounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
``Sscsrind`` Supported
``Ssqosid`` Assembly Support
``Ssstateen`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
``Ssstrict`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
``Sstc`` Assembly Support
Expand Down Expand Up @@ -290,9 +291,6 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-ssnpm``, ``experimental-smnpm``, ``experimental-smmpm``, ``experimental-sspm``, ``experimental-supm``
LLVM implements the `v1.0.0-rc2 specification <https://github.com/riscv/riscv-j-extension/releases/tag/pointer-masking-v1.0.0-rc2>`__.

``experimental-ssqosid``
LLVM implements assembler support for the `v1.0-rc1 draft specification <https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0-rc1>`_.

``experimental-zacas``
LLVM implements the `1.0 release specification <https://github.com/riscvarchive/riscv-zacas/releases/tag/v1.0>`__. amocas.w will be used for i32 cmpxchg. amocas.d will be used i64 cmpxchg on RV64. The compiler will not generate amocas.d on RV32 or amocas.q on RV64 due to ABI compatibilty. These can only be used in the assembler. The extension will be left as experimental until `an ABI issue <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/444>`__ is resolved.

Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/RISCV/RISCVFeatures.td
Original file line number Diff line number Diff line change
Expand Up @@ -968,9 +968,9 @@ def FeatureStdExtSstc
: RISCVExtension<"sstc", 1, 0,
"'Sstc' (Supervisor-mode timer interrupts)">;

def FeaturesStdExtSsqosid
: RISCVExperimentalExtension<"ssqosid", 1, 0,
"'Ssqosid' (Quality-of-Service (QoS) Identifiers)">;
def FeatureStdExtSsqosid
: RISCVExtension<"ssqosid", 1, 0,
"'Ssqosid' (Quality-of-Service (QoS) Identifiers)">;

def FeatureStdExtShtvala
: RISCVExtension<"shtvala", 1, 0,
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/attributes.ll
Original file line number Diff line number Diff line change
Expand Up @@ -115,6 +115,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s
; RUN: llc -mtriple=riscv32 -mattr=+smcsrind %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCSRIND %s
; RUN: llc -mtriple=riscv32 -mattr=+sscsrind %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCSRIND %s
; RUN: llc -mtriple=riscv32 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s
; RUN: llc -mtriple=riscv32 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCDELEG %s
; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s
; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s
Expand All @@ -132,7 +133,6 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV32SMMPM %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-sspm %s -o - | FileCheck --check-prefix=RV32SSPM %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV32SUPM %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s

; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
Expand Down Expand Up @@ -256,6 +256,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s
; RUN: llc -mtriple=riscv64 -mattr=+smcsrind %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCSRIND %s
; RUN: llc -mtriple=riscv64 -mattr=+sscsrind %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCSRIND %s
; RUN: llc -mtriple=riscv64 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s
; RUN: llc -mtriple=riscv64 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCDELEG %s
; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s
; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s
Expand All @@ -272,7 +273,6 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV64SMMPM %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-sspm %s -o - | FileCheck --check-prefix=RV64SSPM %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV64SUPM %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s

; Tests for profile features.
; RUN: llc -mtriple=riscv32 -mattr=+rvi20u32 %s -o - | FileCheck --check-prefix=RVI20U32 %s
Expand Down Expand Up @@ -403,6 +403,7 @@
; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
; RV32SMCSRIND: .attribute 5, "rv32i2p1_smcsrind1p0"
; RV32SSCSRIND: .attribute 5, "rv32i2p1_sscsrind1p0"
; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"
; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0"
; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
Expand All @@ -420,7 +421,6 @@
; RV32SMMPM: .attribute 5, "rv32i2p1_smmpm1p0"
; RV32SSPM: .attribute 5, "rv32i2p1_sspm1p0"
; RV32SUPM: .attribute 5, "rv32i2p1_supm1p0"
; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"

; RV64M: .attribute 5, "rv64i2p1_m2p0_zmmul1p0"
; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
Expand Down Expand Up @@ -542,6 +542,7 @@
; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
; RV64SMCSRIND: .attribute 5, "rv64i2p1_smcsrind1p0"
; RV64SSCSRIND: .attribute 5, "rv64i2p1_sscsrind1p0"
; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0"
; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"
Expand All @@ -558,7 +559,6 @@
; RV64SMMPM: .attribute 5, "rv64i2p1_smmpm1p0"
; RV64SSPM: .attribute 5, "rv64i2p1_sspm1p0"
; RV64SUPM: .attribute 5, "rv64i2p1_supm1p0"
; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"

; RVI20U32: .attribute 5, "rv32i2p1"
; RVI20U64: .attribute 5, "rv64i2p1"
Expand Down
2 changes: 1 addition & 1 deletion llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1071,6 +1071,7 @@ R"(All available -march extensions for RISC-V
sscofpmf 1.0
sscounterenw 1.0
sscsrind 1.0
ssqosid 1.0
ssstateen 1.0
ssstrict 1.0
sstc 1.0
Expand Down Expand Up @@ -1123,7 +1124,6 @@ Experimental extensions
smnpm 1.0
ssnpm 1.0
sspm 1.0
ssqosid 1.0
supm 1.0

Supported Profiles
Expand Down
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