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[AArch64] Add support for ACTLR_EL12 system register #105497

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Merged
merged 1 commit into from
Aug 21, 2024
Merged

[AArch64] Add support for ACTLR_EL12 system register #105497

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1 change: 1 addition & 0 deletions llvm/lib/Target/AArch64/AArch64SystemOperands.td
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Original file line number Diff line number Diff line change
Expand Up @@ -939,6 +939,7 @@ def : RWSysReg<"SCTLR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b000>;
def : RWSysReg<"SCTLR_EL2", 0b11, 0b100, 0b0001, 0b0000, 0b000>;
def : RWSysReg<"SCTLR_EL3", 0b11, 0b110, 0b0001, 0b0000, 0b000>;
def : RWSysReg<"ACTLR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b001>;
def : RWSysReg<"ACTLR_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b001>;
def : RWSysReg<"ACTLR_EL2", 0b11, 0b100, 0b0001, 0b0000, 0b001>;
def : RWSysReg<"ACTLR_EL3", 0b11, 0b110, 0b0001, 0b0000, 0b001>;
def : RWSysReg<"HCR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b000>;
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4 changes: 4 additions & 0 deletions llvm/test/MC/AArch64/arm64-system-encoding.s
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Expand Up @@ -59,6 +59,7 @@ foo:
; MSR/MRS instructions
;-----------------------------------------------------------------------------
msr ACTLR_EL1, x3
msr ACTLR_EL12, x3
msr ACTLR_EL2, x3
msr ACTLR_EL3, x3
msr AFSR0_EL1, x3
Expand Down Expand Up @@ -167,6 +168,7 @@ foo:
msr S0_0_C0_C0_0, x0
msr S1_2_C3_C4_5, x2
; CHECK: msr ACTLR_EL1, x3 ; encoding: [0x23,0x10,0x18,0xd5]
; CHECK: msr ACTLR_EL12, x3 ; encoding: [0x23,0x10,0x1d,0xd5]
; CHECK: msr ACTLR_EL2, x3 ; encoding: [0x23,0x10,0x1c,0xd5]
; CHECK: msr ACTLR_EL3, x3 ; encoding: [0x23,0x10,0x1e,0xd5]
; CHECK: msr AFSR0_EL1, x3 ; encoding: [0x03,0x51,0x18,0xd5]
Expand Down Expand Up @@ -280,6 +282,7 @@ foo:
; CHECK-ERRORS: :[[@LINE-1]]:7: error: expected writable system register or pstate

mrs x3, ACTLR_EL1
mrs x3, ACTLR_EL12
mrs x3, ACTLR_EL2
mrs x3, ACTLR_EL3
mrs x3, AFSR0_EL1
Expand Down Expand Up @@ -501,6 +504,7 @@ foo:
mrs x3, S3_3_c11_c1_4

; CHECK: mrs x3, ACTLR_EL1 ; encoding: [0x23,0x10,0x38,0xd5]
; CHECK: mrs x3, ACTLR_EL12 ; encoding: [0x23,0x10,0x3d,0xd5]
; CHECK: mrs x3, ACTLR_EL2 ; encoding: [0x23,0x10,0x3c,0xd5]
; CHECK: mrs x3, ACTLR_EL3 ; encoding: [0x23,0x10,0x3e,0xd5]
; CHECK: mrs x3, AFSR0_EL1 ; encoding: [0x03,0x51,0x38,0xd5]
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4 changes: 4 additions & 0 deletions llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
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Expand Up @@ -3245,6 +3245,7 @@
# CHECK: msr {{sctlr_el2|SCTLR_EL2}}, x12
# CHECK: msr {{sctlr_el3|SCTLR_EL3}}, x12
# CHECK: msr {{actlr_el1|ACTLR_EL1}}, x12
# CHECK: msr {{actlr_el12|ACTLR_EL12}}, x12
# CHECK: msr {{actlr_el2|ACTLR_EL2}}, x12
# CHECK: msr {{actlr_el3|ACTLR_EL3}}, x12
# CHECK: msr {{cpacr_el1|CPACR_EL1}}, x12
Expand Down Expand Up @@ -3575,6 +3576,7 @@
# CHECK: mrs x9, {{sctlr_el2|SCTLR_EL2}}
# CHECK: mrs x9, {{sctlr_el3|SCTLR_EL3}}
# CHECK: mrs x9, {{actlr_el1|ACTLR_EL1}}
# CHECK: mrs x9, {{actlr_el12|ACTLR_EL12}}
# CHECK: mrs x9, {{actlr_el2|ACTLR_EL2}}
# CHECK: mrs x9, {{actlr_el3|ACTLR_EL3}}
# CHECK: mrs x9, {{cpacr_el1|CPACR_EL1}}
Expand Down Expand Up @@ -3867,6 +3869,7 @@
0xc 0x10 0x1c 0xd5
0xc 0x10 0x1e 0xd5
0x2c 0x10 0x18 0xd5
0x2c 0x10 0x1d 0xd5
0x2c 0x10 0x1c 0xd5
0x2c 0x10 0x1e 0xd5
0x4c 0x10 0x18 0xd5
Expand Down Expand Up @@ -4199,6 +4202,7 @@
0x9 0x10 0x3c 0xd5
0x9 0x10 0x3e 0xd5
0x29 0x10 0x38 0xd5
0x29 0x10 0x3d 0xd5
0x29 0x10 0x3c 0xd5
0x29 0x10 0x3e 0xd5
0x49 0x10 0x38 0xd5
Expand Down
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