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[AMDGPU] Remove dead pass: AMDGPUMachineCFGStructurizer #105645

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Merged
merged 1 commit into from
Aug 23, 2024
Merged

[AMDGPU] Remove dead pass: AMDGPUMachineCFGStructurizer #105645

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4 changes: 0 additions & 4 deletions llvm/lib/Target/AMDGPU/AMDGPU.h
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Original file line number Diff line number Diff line change
Expand Up @@ -57,7 +57,6 @@ FunctionPass *createAMDGPUImageIntrinsicOptimizerPass(const TargetMachine *);
ModulePass *createAMDGPURemoveIncompatibleFunctionsPass(const TargetMachine *);
FunctionPass *createAMDGPUCodeGenPreparePass();
FunctionPass *createAMDGPULateCodeGenPrepareLegacyPass();
FunctionPass *createAMDGPUMachineCFGStructurizerPass();
FunctionPass *createAMDGPURewriteOutArgumentsPass();
ModulePass *
createAMDGPULowerModuleLDSLegacyPass(const AMDGPUTargetMachine *TM = nullptr);
Expand Down Expand Up @@ -92,9 +91,6 @@ class SILowerI1CopiesPass : public PassInfoMixin<SILowerI1CopiesPass> {

void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &);

void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&);
extern char &AMDGPUMachineCFGStructurizerID;

void initializeAMDGPUAlwaysInlinePass(PassRegistry&);

Pass *createAMDGPUAnnotateKernelFeaturesPass();
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3 changes: 0 additions & 3 deletions llvm/lib/Target/AMDGPU/AMDGPU.td
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Expand Up @@ -2253,9 +2253,6 @@ def HasDefaultComponentBroadcast
def HasDsSrc2Insts : Predicate<"!Subtarget->hasDsSrc2Insts()">,
AssemblerPredicate<(all_of FeatureDsSrc2Insts)>;

def EnableLateCFGStructurize : Predicate<
"EnableLateStructurizeCFG">;

def EnableFlatScratch : Predicate<"Subtarget->enableFlatScratch()">;

def DisableFlatScratch : Predicate<"!Subtarget->enableFlatScratch()">;
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4 changes: 1 addition & 3 deletions llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
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Expand Up @@ -121,9 +121,7 @@ FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM,

AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM,
CodeGenOptLevel OptLevel)
: SelectionDAGISel(TM, OptLevel) {
EnableLateStructurizeCFG = AMDGPUTargetMachine::EnableLateStructurizeCFG;
}
: SelectionDAGISel(TM, OptLevel) {}

bool AMDGPUDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
Subtarget = &MF.getSubtarget<GCNSubtarget>();
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2 changes: 0 additions & 2 deletions llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
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Expand Up @@ -68,8 +68,6 @@ class AMDGPUDAGToDAGISel : public SelectionDAGISel {
// Default FP mode for the current function.
SIModeRegisterDefaults Mode;

bool EnableLateStructurizeCFG;

// Instructions that will be lowered with a final instruction that zeros the
// high result bits.
bool fp16SrcZerosHighBits(unsigned Opc) const;
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1 change: 0 additions & 1 deletion llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
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Expand Up @@ -45,7 +45,6 @@ AMDGPUInstructionSelector::AMDGPUInstructionSelector(
const AMDGPUTargetMachine &TM)
: TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI), TM(TM),
STI(STI),
EnableLateStructurizeCFG(AMDGPUTargetMachine::EnableLateStructurizeCFG),
#define GET_GLOBALISEL_PREDICATES_INIT
#include "AMDGPUGenGlobalISel.inc"
#undef GET_GLOBALISEL_PREDICATES_INIT
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1 change: 0 additions & 1 deletion llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
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Expand Up @@ -371,7 +371,6 @@ class AMDGPUInstructionSelector final : public InstructionSelector {
const AMDGPURegisterBankInfo &RBI;
const AMDGPUTargetMachine &TM;
const GCNSubtarget &STI;
bool EnableLateStructurizeCFG;
#define GET_GLOBALISEL_PREDICATES_DECL
#define AMDGPUSubtarget GCNSubtarget
#include "AMDGPUGenGlobalISel.inc"
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