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[RISCV][GISel] Use CCValAssign::getCustomReg for converting f16/f32<->GPR. #105700

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Merged
merged 4 commits into from
Sep 4, 2024
Merged

[RISCV][GISel] Use CCValAssign::getCustomReg for converting f16/f32<->GPR. #105700

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e5b0334
[RISCV][GISel] Use CCValAssign::getCustomReg for converting f16/f32<-…
topperc Aug 20, 2024
8cf6f06
fixup! Reduce the changes to gisel.
topperc Aug 22, 2024
c58c04b
Merge remote-tracking branch 'origin/main' into pr/custom-reg
topperc Aug 27, 2024
0824b6e
fixup! Rebase on FastCC change
topperc Aug 27, 2024
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61 changes: 42 additions & 19 deletions llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -103,15 +103,6 @@ struct RISCVOutgoingValueHandler : public CallLowering::OutgoingValueHandler {

void assignValueToReg(Register ValVReg, Register PhysReg,
const CCValAssign &VA) override {
// If we're passing a smaller fp value into a larger integer register,
// anyextend before copying.
if ((VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) ||
((VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::i64) &&
VA.getValVT() == MVT::f16)) {
LLT DstTy = LLT::scalar(VA.getLocVT().getSizeInBits());
ValVReg = MIRBuilder.buildAnyExt(DstTy, ValVReg).getReg(0);
}

Register ExtReg = extendRegister(ValVReg, VA);
MIRBuilder.buildCopy(PhysReg, ExtReg);
MIB.addUse(PhysReg, RegState::Implicit);
Expand All @@ -120,16 +111,35 @@ struct RISCVOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
unsigned assignCustomValue(CallLowering::ArgInfo &Arg,
ArrayRef<CCValAssign> VAs,
std::function<void()> *Thunk) override {
const CCValAssign &VA = VAs[0];
if ((VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) ||
(VA.getLocVT().isInteger() && VA.getValVT() == MVT::f16)) {
Register PhysReg = VA.getLocReg();

auto assignFunc = [=]() {
auto Trunc = MIRBuilder.buildAnyExt(LLT(VA.getLocVT()), Arg.Regs[0]);
MIRBuilder.buildCopy(PhysReg, Trunc);
MIB.addUse(PhysReg, RegState::Implicit);
};

if (Thunk) {
*Thunk = assignFunc;
return 1;
}

assignFunc();
return 1;
}

assert(VAs.size() >= 2 && "Expected at least 2 VAs.");
const CCValAssign &VALo = VAs[0];
const CCValAssign &VAHi = VAs[1];

assert(VAHi.needsCustom() && "Value doesn't need custom handling");
assert(VALo.getValNo() == VAHi.getValNo() &&
assert(VA.getValNo() == VAHi.getValNo() &&
"Values belong to different arguments");

assert(VALo.getLocVT() == MVT::i32 && VAHi.getLocVT() == MVT::i32 &&
VALo.getValVT() == MVT::f64 && VAHi.getValVT() == MVT::f64 &&
assert(VA.getLocVT() == MVT::i32 && VAHi.getLocVT() == MVT::i32 &&
VA.getValVT() == MVT::f64 && VAHi.getValVT() == MVT::f64 &&
"unexpected custom value");

Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
Expand All @@ -148,7 +158,7 @@ struct RISCVOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
}

auto assignFunc = [=]() {
assignValueToReg(NewRegs[0], VALo.getLocReg(), VALo);
assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
if (VAHi.isRegLoc())
assignValueToReg(NewRegs[1], VAHi.getLocReg(), VAHi);
};
Expand Down Expand Up @@ -246,16 +256,29 @@ struct RISCVIncomingValueHandler : public CallLowering::IncomingValueHandler {
unsigned assignCustomValue(CallLowering::ArgInfo &Arg,
ArrayRef<CCValAssign> VAs,
std::function<void()> *Thunk) override {
const CCValAssign &VA = VAs[0];
if ((VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) ||
(VA.getLocVT().isInteger() && VA.getValVT() == MVT::f16)) {
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maybe consider bfloat but I guess that's totally busted in globalisel anyway

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I'll do it as a separate patch. I don't think it belongs in this one.

Register PhysReg = VA.getLocReg();

markPhysRegUsed(PhysReg);

LLT LocTy(VA.getLocVT());
auto Copy = MIRBuilder.buildCopy(LocTy, PhysReg);

MIRBuilder.buildTrunc(Arg.Regs[0], Copy.getReg(0));
return 1;
}

assert(VAs.size() >= 2 && "Expected at least 2 VAs.");
const CCValAssign &VALo = VAs[0];
const CCValAssign &VAHi = VAs[1];

assert(VAHi.needsCustom() && "Value doesn't need custom handling");
assert(VALo.getValNo() == VAHi.getValNo() &&
assert(VA.getValNo() == VAHi.getValNo() &&
"Values belong to different arguments");

assert(VALo.getLocVT() == MVT::i32 && VAHi.getLocVT() == MVT::i32 &&
VALo.getValVT() == MVT::f64 && VAHi.getValVT() == MVT::f64 &&
assert(VA.getLocVT() == MVT::i32 && VAHi.getLocVT() == MVT::i32 &&
VA.getValVT() == MVT::f64 && VAHi.getValVT() == MVT::f64 &&
"unexpected custom value");

Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
Expand All @@ -272,7 +295,7 @@ struct RISCVIncomingValueHandler : public CallLowering::IncomingValueHandler {
const_cast<CCValAssign &>(VAHi));
}

assignValueToReg(NewRegs[0], VALo.getLocReg(), VALo);
assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
if (VAHi.isRegLoc())
assignValueToReg(NewRegs[1], VAHi.getLocReg(), VAHi);

Expand Down
68 changes: 46 additions & 22 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -18672,6 +18672,19 @@ bool RISCV::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
// similar local variables rather than directly checking against the target
// ABI.

ArrayRef<MCPhysReg> ArgGPRs = RISCV::getArgGPRs(ABI);

if (UseGPRForF16_F32 && (ValVT == MVT::f16 || ValVT == MVT::bf16 ||
(ValVT == MVT::f32 && XLen == 64))) {
Register Reg = State.AllocateReg(ArgGPRs);
if (Reg) {
LocVT = XLenVT;
State.addLoc(
CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
}

if (UseGPRForF16_F32 &&
(ValVT == MVT::f16 || ValVT == MVT::bf16 || ValVT == MVT::f32)) {
LocVT = XLenVT;
Expand All @@ -18681,8 +18694,6 @@ bool RISCV::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
LocInfo = CCValAssign::BCvt;
}

ArrayRef<MCPhysReg> ArgGPRs = RISCV::getArgGPRs(ABI);

// If this is a variadic argument, the RISC-V calling convention requires
// that it is assigned an 'even' or 'aligned' register if it has 8-byte
// alignment (RV32) or 16-byte alignment (RV64). An aligned register should
Expand Down Expand Up @@ -18938,6 +18949,17 @@ void RISCVTargetLowering::analyzeOutputArgs(
static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDValue Val,
const CCValAssign &VA, const SDLoc &DL,
const RISCVSubtarget &Subtarget) {
if (VA.needsCustom()) {
if (VA.getLocVT().isInteger() &&
(VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
Val = DAG.getNode(RISCVISD::FMV_H_X, DL, VA.getValVT(), Val);
else if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32)
Val = DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, Val);
else
llvm_unreachable("Unexpected Custom handling.");
return Val;
}

switch (VA.getLocInfo()) {
default:
llvm_unreachable("Unexpected CCValAssign::LocInfo");
Expand All @@ -18946,14 +18968,7 @@ static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDValue Val,
Val = convertFromScalableVector(VA.getValVT(), Val, DAG, Subtarget);
break;
case CCValAssign::BCvt:
if (VA.getLocVT().isInteger() &&
(VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16)) {
Val = DAG.getNode(RISCVISD::FMV_H_X, DL, VA.getValVT(), Val);
} else if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) {
Val = DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, Val);
} else {
Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
}
Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
break;
}
return Val;
Expand Down Expand Up @@ -18999,6 +19014,17 @@ static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDValue Val,
const RISCVSubtarget &Subtarget) {
EVT LocVT = VA.getLocVT();

if (VA.needsCustom()) {
if (LocVT.isInteger() &&
(VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
Val = DAG.getNode(RISCVISD::FMV_X_ANYEXTH, DL, LocVT, Val);
else if (LocVT == MVT::i64 && VA.getValVT() == MVT::f32)
Val = DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Val);
else
llvm_unreachable("Unexpected Custom handling.");
return Val;
}

switch (VA.getLocInfo()) {
default:
llvm_unreachable("Unexpected CCValAssign::LocInfo");
Expand All @@ -19007,14 +19033,7 @@ static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDValue Val,
Val = convertToScalableVector(LocVT, Val, DAG, Subtarget);
break;
case CCValAssign::BCvt:
if (LocVT.isInteger() &&
(VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16)) {
Val = DAG.getNode(RISCVISD::FMV_X_ANYEXTH, DL, LocVT, Val);
} else if (LocVT == MVT::i64 && VA.getValVT() == MVT::f32) {
Val = DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Val);
} else {
Val = DAG.getNode(ISD::BITCAST, DL, LocVT, Val);
}
Val = DAG.getNode(ISD::BITCAST, DL, LocVT, Val);
break;
}
return Val;
Expand Down Expand Up @@ -19148,8 +19167,14 @@ bool RISCV::CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI,
(LocVT == MVT::f64 && Subtarget.is64Bit() &&
Subtarget.hasStdExtZdinx())) {
if (MCRegister Reg = State.AllocateReg(getFastCCArgGPRs(ABI))) {
LocInfo = CCValAssign::BCvt;
if (LocVT.getSizeInBits() != Subtarget.getXLen()) {
LocVT = Subtarget.getXLenVT();
State.addLoc(
CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
LocVT = Subtarget.getXLenVT();
LocInfo = CCValAssign::BCvt;
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
Expand Down Expand Up @@ -19793,9 +19818,8 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
Glue = RetValue2.getValue(2);
RetValue = DAG.getNode(RISCVISD::BuildPairF64, DL, MVT::f64, RetValue,
RetValue2);
}

RetValue = convertLocVTToValVT(DAG, RetValue, VA, DL, Subtarget);
} else
RetValue = convertLocVTToValVT(DAG, RetValue, VA, DL, Subtarget);

InVals.push_back(RetValue);
}
Expand Down
9 changes: 4 additions & 5 deletions llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1018,7 +1018,6 @@ define half @caller_half_return_stack2(half %x, half %y) nounwind {
; RV64IF-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
; RV64IF-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
; RV64IF-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
; RV64IF-NEXT: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
; RV64IF-NEXT: $f10_f = COPY [[ANYEXT]](s32)
; RV64IF-NEXT: $f11_f = COPY [[ANYEXT1]](s32)
; RV64IF-NEXT: $f12_f = COPY [[ANYEXT2]](s32)
Expand All @@ -1027,14 +1026,14 @@ define half @caller_half_return_stack2(half %x, half %y) nounwind {
; RV64IF-NEXT: $f15_f = COPY [[ANYEXT5]](s32)
; RV64IF-NEXT: $f16_f = COPY [[ANYEXT6]](s32)
; RV64IF-NEXT: $f17_f = COPY [[ANYEXT7]](s32)
; RV64IF-NEXT: [[ANYEXT9:%[0-9]+]]:_(s64) = G_ANYEXT [[ANYEXT8]](s32)
; RV64IF-NEXT: $x10 = COPY [[ANYEXT9]](s64)
; RV64IF-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s16)
; RV64IF-NEXT: $x10 = COPY [[ANYEXT8]](s64)
; RV64IF-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack2, csr_ilp32f_lp64f, implicit-def $x1, implicit $f10_f, implicit $f11_f, implicit $f12_f, implicit $f13_f, implicit $f14_f, implicit $f15_f, implicit $f16_f, implicit $f17_f, implicit $x10, implicit-def $f10_f
; RV64IF-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
; RV64IF-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f10_f
; RV64IF-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
; RV64IF-NEXT: [[ANYEXT10:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC2]](s16)
; RV64IF-NEXT: $f10_f = COPY [[ANYEXT10]](s32)
; RV64IF-NEXT: [[ANYEXT9:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC2]](s16)
; RV64IF-NEXT: $f10_f = COPY [[ANYEXT9]](s32)
; RV64IF-NEXT: PseudoRET implicit $f10_f
;
; RV64IZFH-LABEL: name: caller_half_return_stack2
Expand Down
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