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[AMDGPU] Fix sign confusion in performMulLoHiCombine #105831

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merged 2 commits into from
Aug 27, 2024
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[AMDGPU] Fix sign confusion in performMulLoHiCombine #105831

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a2ea3b6
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jayfoad Aug 23, 2024
718d953
[AMDGPU] Fix sign confusion in performMulLoHiCombine
jayfoad Aug 23, 2024
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30 changes: 18 additions & 12 deletions llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4346,6 +4346,7 @@ AMDGPUTargetLowering::performMulLoHiCombine(SDNode *N,
SelectionDAG &DAG = DCI.DAG;
SDLoc DL(N);

bool Signed = N->getOpcode() == ISD::SMUL_LOHI;
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);

Expand All @@ -4360,20 +4361,25 @@ AMDGPUTargetLowering::performMulLoHiCombine(SDNode *N,

// Try to use two fast 24-bit multiplies (one for each half of the result)
// instead of one slow extending multiply.
unsigned LoOpcode, HiOpcode;
if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
LoOpcode = AMDGPUISD::MUL_U24;
HiOpcode = AMDGPUISD::MULHI_U24;
} else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
LoOpcode = AMDGPUISD::MUL_I24;
HiOpcode = AMDGPUISD::MULHI_I24;
unsigned LoOpcode = 0;
unsigned HiOpcode = 0;
if (Signed) {
if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
LoOpcode = AMDGPUISD::MUL_I24;
HiOpcode = AMDGPUISD::MULHI_I24;
}
} else {
return SDValue();
if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
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} else if {

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Don't you like symmetry?!

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I do, but I don't like else { if .... But up to you, really.

N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
LoOpcode = AMDGPUISD::MUL_U24;
HiOpcode = AMDGPUISD::MULHI_U24;
}
}
if (!LoOpcode)
return SDValue();

SDValue Lo = DAG.getNode(LoOpcode, DL, MVT::i32, N0, N1);
SDValue Hi = DAG.getNode(HiOpcode, DL, MVT::i32, N0, N1);
Expand Down
108 changes: 56 additions & 52 deletions llvm/test/CodeGen/AMDGPU/div-rem-by-constant-64.ll
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Expand Up @@ -1052,21 +1052,22 @@ define noundef i64 @srem64_i32max(i64 noundef %i) {
; GFX9-NEXT: s_mov_b32 s6, 0x80000001
; GFX9-NEXT: v_ashrrev_i32_e32 v6, 31, v1
; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, 3, v[2:3]
; GFX9-NEXT: v_mul_i32_i24_e32 v2, 3, v6
; GFX9-NEXT: v_mul_hi_i32_i24_e32 v7, 3, v6
; GFX9-NEXT: v_mov_b32_e32 v8, v5
; GFX9-NEXT: v_mul_i32_i24_e32 v8, 3, v6
; GFX9-NEXT: v_lshl_add_u32 v9, v6, 31, v6
; GFX9-NEXT: v_mov_b32_e32 v10, v5
; GFX9-NEXT: v_mov_b32_e32 v5, v3
; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v0, s6, v[4:5]
; GFX9-NEXT: v_lshl_add_u32 v6, v6, 31, v6
; GFX9-NEXT: v_add3_u32 v3, v7, v6, v2
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v8, v4
; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, -1, v[2:3]
; GFX9-NEXT: v_addc_co_u32_e64 v5, s[4:5], 0, 0, vcc
; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, s6, v[4:5]
; GFX9-NEXT: v_sub_u32_e32 v3, v3, v1
; GFX9-NEXT: v_sub_u32_e32 v3, v3, v0
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v3, vcc
; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, s6, v[4:5]
; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v6, 3, 0
; GFX9-NEXT: v_mov_b32_e32 v2, v3
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v10, v2
; GFX9-NEXT: v_add3_u32 v7, v7, v9, v8
; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v0, -1, v[6:7]
; GFX9-NEXT: v_addc_co_u32_e64 v3, s[4:5], 0, 0, vcc
; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, s6, v[2:3]
; GFX9-NEXT: v_sub_u32_e32 v5, v5, v1
; GFX9-NEXT: v_sub_u32_e32 v5, v5, v0
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v5, vcc
; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, 1, v[2:3]
; GFX9-NEXT: s_brev_b32 s6, -2
; GFX9-NEXT: v_add_u32_e32 v3, v1, v3
Expand All @@ -1083,11 +1084,11 @@ define noundef i64 @srem64_i32max(i64 noundef %i) {
; GFX942-LABEL: srem64_i32max:
; GFX942: ; %bb.0: ; %entry
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: v_ashrrev_i32_e32 v3, 31, v1
; GFX942-NEXT: v_mul_i32_i24_e32 v2, 3, v3
; GFX942-NEXT: v_mul_hi_i32_i24_e32 v4, 3, v3
; GFX942-NEXT: v_lshl_add_u32 v3, v3, 31, v3
; GFX942-NEXT: v_add3_u32 v3, v4, v3, v2
; GFX942-NEXT: v_ashrrev_i32_e32 v2, 31, v1
; GFX942-NEXT: v_mul_i32_i24_e32 v4, 3, v2
; GFX942-NEXT: v_lshl_add_u32 v5, v2, 31, v2
; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v2, 3, 0
; GFX942-NEXT: v_add3_u32 v3, v3, v5, v4
; GFX942-NEXT: v_mul_hi_u32 v4, v0, 3
; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: v_mad_u64_u32 v[6:7], s[0:1], v1, 3, v[4:5]
Expand Down Expand Up @@ -1124,16 +1125,17 @@ define noundef i64 @srem64_i32max(i64 noundef %i) {
; GFX1030-NEXT: v_mul_hi_u32 v2, v0, 3
; GFX1030-NEXT: v_mov_b32_e32 v3, 0
; GFX1030-NEXT: v_ashrrev_i32_e32 v6, 31, v1
; GFX1030-NEXT: v_mul_hi_i32_i24_e32 v8, 3, v6
; GFX1030-NEXT: v_mul_i32_i24_e32 v7, 3, v6
; GFX1030-NEXT: v_mad_u64_u32 v[4:5], null, v1, 3, v[2:3]
; GFX1030-NEXT: v_mul_i32_i24_e32 v2, 3, v6
; GFX1030-NEXT: v_lshl_add_u32 v6, v6, 31, v6
; GFX1030-NEXT: v_mov_b32_e32 v7, v5
; GFX1030-NEXT: v_mov_b32_e32 v8, v5
; GFX1030-NEXT: v_mov_b32_e32 v5, v3
; GFX1030-NEXT: v_mad_u64_u32 v[3:4], null, 0x80000001, v0, v[4:5]
; GFX1030-NEXT: v_add3_u32 v3, v8, v6, v2
; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, v6, 3, 0
; GFX1030-NEXT: v_lshl_add_u32 v6, v6, 31, v6
; GFX1030-NEXT: v_mad_u64_u32 v[4:5], null, 0x80000001, v0, v[4:5]
; GFX1030-NEXT: v_add3_u32 v3, v3, v6, v7
; GFX1030-NEXT: v_mov_b32_e32 v4, v5
; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, v0, -1, v[2:3]
; GFX1030-NEXT: v_add_co_u32 v4, s4, v7, v4
; GFX1030-NEXT: v_add_co_u32 v4, s4, v8, v4
; GFX1030-NEXT: v_add_co_ci_u32_e64 v5, null, 0, 0, s4
; GFX1030-NEXT: v_sub_nc_u32_e32 v6, v3, v1
; GFX1030-NEXT: v_mad_u64_u32 v[3:4], null, 0x80000001, v1, v[4:5]
Expand Down Expand Up @@ -1165,21 +1167,22 @@ define noundef i64 @sdiv64_i32max(i64 noundef %i) {
; GFX9-NEXT: s_mov_b32 s6, 0x80000001
; GFX9-NEXT: v_ashrrev_i32_e32 v6, 31, v1
; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, 3, v[2:3]
; GFX9-NEXT: v_mul_i32_i24_e32 v2, 3, v6
; GFX9-NEXT: v_mul_hi_i32_i24_e32 v7, 3, v6
; GFX9-NEXT: v_mov_b32_e32 v8, v5
; GFX9-NEXT: v_mul_i32_i24_e32 v8, 3, v6
; GFX9-NEXT: v_lshl_add_u32 v9, v6, 31, v6
; GFX9-NEXT: v_mov_b32_e32 v10, v5
; GFX9-NEXT: v_mov_b32_e32 v5, v3
; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v0, s6, v[4:5]
; GFX9-NEXT: v_lshl_add_u32 v6, v6, 31, v6
; GFX9-NEXT: v_add3_u32 v3, v7, v6, v2
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v8, v4
; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, -1, v[2:3]
; GFX9-NEXT: v_addc_co_u32_e64 v5, s[4:5], 0, 0, vcc
; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, s6, v[4:5]
; GFX9-NEXT: v_sub_u32_e32 v3, v3, v1
; GFX9-NEXT: v_sub_u32_e32 v3, v3, v0
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v3, vcc
; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, s6, v[4:5]
; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v6, 3, 0
; GFX9-NEXT: v_mov_b32_e32 v2, v3
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v10, v2
; GFX9-NEXT: v_add3_u32 v7, v7, v9, v8
; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v0, -1, v[6:7]
; GFX9-NEXT: v_addc_co_u32_e64 v3, s[4:5], 0, 0, vcc
; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, s6, v[2:3]
; GFX9-NEXT: v_sub_u32_e32 v5, v5, v1
; GFX9-NEXT: v_sub_u32_e32 v5, v5, v0
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v5, vcc
; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, 1, v[2:3]
; GFX9-NEXT: v_add_u32_e32 v3, v1, v3
; GFX9-NEXT: v_ashrrev_i64 v[0:1], 30, v[2:3]
Expand All @@ -1191,11 +1194,11 @@ define noundef i64 @sdiv64_i32max(i64 noundef %i) {
; GFX942-LABEL: sdiv64_i32max:
; GFX942: ; %bb.0: ; %entry
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: v_ashrrev_i32_e32 v3, 31, v1
; GFX942-NEXT: v_mul_i32_i24_e32 v2, 3, v3
; GFX942-NEXT: v_mul_hi_i32_i24_e32 v4, 3, v3
; GFX942-NEXT: v_lshl_add_u32 v3, v3, 31, v3
; GFX942-NEXT: v_add3_u32 v3, v4, v3, v2
; GFX942-NEXT: v_ashrrev_i32_e32 v2, 31, v1
; GFX942-NEXT: v_mul_i32_i24_e32 v4, 3, v2
; GFX942-NEXT: v_lshl_add_u32 v5, v2, 31, v2
; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v2, 3, 0
; GFX942-NEXT: v_add3_u32 v3, v3, v5, v4
; GFX942-NEXT: v_mul_hi_u32 v4, v0, 3
; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: v_mad_u64_u32 v[6:7], s[0:1], v1, 3, v[4:5]
Expand Down Expand Up @@ -1224,16 +1227,17 @@ define noundef i64 @sdiv64_i32max(i64 noundef %i) {
; GFX1030-NEXT: v_mul_hi_u32 v2, v0, 3
; GFX1030-NEXT: v_mov_b32_e32 v3, 0
; GFX1030-NEXT: v_ashrrev_i32_e32 v6, 31, v1
; GFX1030-NEXT: v_mul_hi_i32_i24_e32 v8, 3, v6
; GFX1030-NEXT: v_mul_i32_i24_e32 v7, 3, v6
; GFX1030-NEXT: v_mad_u64_u32 v[4:5], null, v1, 3, v[2:3]
; GFX1030-NEXT: v_mul_i32_i24_e32 v2, 3, v6
; GFX1030-NEXT: v_lshl_add_u32 v6, v6, 31, v6
; GFX1030-NEXT: v_mov_b32_e32 v7, v5
; GFX1030-NEXT: v_mov_b32_e32 v8, v5
; GFX1030-NEXT: v_mov_b32_e32 v5, v3
; GFX1030-NEXT: v_mad_u64_u32 v[3:4], null, 0x80000001, v0, v[4:5]
; GFX1030-NEXT: v_add3_u32 v3, v8, v6, v2
; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, v6, 3, 0
; GFX1030-NEXT: v_lshl_add_u32 v6, v6, 31, v6
; GFX1030-NEXT: v_mad_u64_u32 v[4:5], null, 0x80000001, v0, v[4:5]
; GFX1030-NEXT: v_add3_u32 v3, v3, v6, v7
; GFX1030-NEXT: v_mov_b32_e32 v4, v5
; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, v0, -1, v[2:3]
; GFX1030-NEXT: v_add_co_u32 v4, s4, v7, v4
; GFX1030-NEXT: v_add_co_u32 v4, s4, v8, v4
; GFX1030-NEXT: v_add_co_ci_u32_e64 v5, null, 0, 0, s4
; GFX1030-NEXT: v_sub_nc_u32_e32 v6, v3, v1
; GFX1030-NEXT: v_mad_u64_u32 v[3:4], null, 0x80000001, v1, v[4:5]
Expand Down
98 changes: 98 additions & 0 deletions llvm/test/CodeGen/AMDGPU/mul_int24.ll
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Expand Up @@ -813,4 +813,102 @@ bb7:
ret void

}

define amdgpu_kernel void @test_umul_i24(ptr addrspace(1) %out, i32 %arg) {
; SI-LABEL: test_umul_i24:
; SI: ; %bb.0:
; SI-NEXT: s_load_dword s1, s[2:3], 0xb
; SI-NEXT: v_mov_b32_e32 v0, 0xff803fe1
; SI-NEXT: s_mov_b32 s0, 0
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshr_b32 s1, s1, 9
; SI-NEXT: v_mul_hi_u32 v0, s1, v0
; SI-NEXT: s_mul_i32 s1, s1, 0xff803fe1
; SI-NEXT: v_alignbit_b32 v0, v0, s1, 1
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_mov_b32 s1, s0
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: test_umul_i24:
; VI: ; %bb.0:
; VI-NEXT: s_load_dword s0, s[2:3], 0x2c
; VI-NEXT: v_mov_b32_e32 v0, 0xff803fe1
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_lshr_b32 s0, s0, 9
; VI-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s0, v0, 0
; VI-NEXT: s_mov_b32 s0, 0
; VI-NEXT: s_mov_b32 s1, s0
; VI-NEXT: v_alignbit_b32 v0, v1, v0, 1
; VI-NEXT: s_nop 1
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm
;
; GFX9-LABEL: test_umul_i24:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dword s1, s[2:3], 0x2c
; GFX9-NEXT: s_mov_b32 s0, 0
; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshr_b32 s1, s1, 9
; GFX9-NEXT: s_mul_hi_u32 s4, s1, 0xff803fe1
; GFX9-NEXT: s_mul_i32 s1, s1, 0xff803fe1
; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_alignbit_b32 v0, s4, v0, 1
; GFX9-NEXT: s_mov_b32 s1, s0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm
;
; EG-LABEL: test_umul_i24:
; EG: ; %bb.0:
; EG-NEXT: ALU 8, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
; EG-NEXT: ALU clause starting at 4:
; EG-NEXT: LSHR * T0.W, KC0[2].Z, literal.x,
; EG-NEXT: 9(1.261169e-44), 0(0.000000e+00)
; EG-NEXT: MULHI * T0.X, PV.W, literal.x,
; EG-NEXT: -8372255(nan), 0(0.000000e+00)
; EG-NEXT: MULLO_INT * T0.Y, T0.W, literal.x,
; EG-NEXT: -8372255(nan), 0(0.000000e+00)
; EG-NEXT: BIT_ALIGN_INT T0.X, T0.X, PS, 1,
; EG-NEXT: MOV * T1.X, literal.x,
; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00)
;
; CM-LABEL: test_umul_i24:
; CM: ; %bb.0:
; CM-NEXT: ALU 14, @4, KC0[CB0:0-32], KC1[]
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
; CM-NEXT: CF_END
; CM-NEXT: PAD
; CM-NEXT: ALU clause starting at 4:
; CM-NEXT: LSHR * T0.W, KC0[2].Z, literal.x,
; CM-NEXT: 9(1.261169e-44), 0(0.000000e+00)
; CM-NEXT: MULHI T0.X, T0.W, literal.x,
; CM-NEXT: MULHI T0.Y (MASKED), T0.W, literal.x,
; CM-NEXT: MULHI T0.Z (MASKED), T0.W, literal.x,
; CM-NEXT: MULHI * T0.W (MASKED), T0.W, literal.x,
; CM-NEXT: -8372255(nan), 0(0.000000e+00)
; CM-NEXT: MULLO_INT T0.X (MASKED), T0.W, literal.x,
; CM-NEXT: MULLO_INT T0.Y, T0.W, literal.x,
; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, literal.x,
; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, literal.x,
; CM-NEXT: -8372255(nan), 0(0.000000e+00)
; CM-NEXT: BIT_ALIGN_INT * T0.X, T0.X, PV.Y, 1,
; CM-NEXT: MOV * T1.X, literal.x,
; CM-NEXT: 0(0.000000e+00), 0(0.000000e+00)
%i = lshr i32 %arg, 9
%i1 = zext i32 %i to i64
%i2 = mul i64 %i1, 4286595041
%i3 = lshr i64 %i2, 1
%i4 = trunc i64 %i3 to i32
store i32 %i4, ptr addrspace(1) null, align 4
ret void
}

attributes #0 = { nounwind }
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