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[RISCV] Model dest EEW and fix peepholes not checking EEW #105945

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Merged
merged 4 commits into from
Sep 5, 2024
Merged

[RISCV] Model dest EEW and fix peepholes not checking EEW #105945

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d613f17
Precommit test
lukel97 Aug 24, 2024
5b29e16
[RISCV] Model dest EEW and fix peepholes not checking EEW
lukel97 Aug 24, 2024
8545659
Don't check ratio
lukel97 Aug 29, 2024
e687c08
Address comment, fix mask types not returning log2 EEW
lukel97 Sep 5, 2024
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8 changes: 8 additions & 0 deletions llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
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Expand Up @@ -129,6 +129,14 @@ enum {

ElementsDependOnMaskShift = ElementsDependOnVLShift + 1,
ElementsDependOnMaskMask = 1ULL << ElementsDependOnMaskShift,

// Indicates the EEW of a vector instruction's destination operand.
// 0 -> 1
// 1 -> SEW
// 2 -> SEW * 2
// 3 -> SEW * 4
DestEEWShift = ElementsDependOnMaskShift + 1,
DestEEWMask = 3ULL << DestEEWShift,
};

// Helper functions to read TSFlags.
Expand Down
12 changes: 12 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrFormats.td
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Expand Up @@ -167,6 +167,14 @@ def EltDepsNone : EltDeps<vl=0, mask=0>;
def EltDepsVL : EltDeps<vl=1, mask=0>;
def EltDepsVLMask : EltDeps<vl=1, mask=1>;

class EEW <bits<2> val> {
bits<2> Value = val;
}
def EEW1 : EEW<0>;
def EEWSEWx1 : EEW<1>;
def EEWSEWx2 : EEW<2>;
def EEWSEWx4 : EEW<3>;

class RVInstCommon<dag outs, dag ins, string opcodestr, string argstr,
list<dag> pattern, InstFormat format> : Instruction {
let Namespace = "RISCV";
Expand Down Expand Up @@ -240,6 +248,10 @@ class RVInstCommon<dag outs, dag ins, string opcodestr, string argstr,
EltDeps ElementsDependOn = EltDepsNone;
let TSFlags{23} = ElementsDependOn.VL;
let TSFlags{24} = ElementsDependOn.Mask;

// Indicates the EEW of a vector instruction's destination operand.
EEW DestEEW = EEWSEWx1;
let TSFlags{26-25} = DestEEW.Value;
}

class RVInst<dag outs, dag ins, string opcodestr, string argstr,
Expand Down
12 changes: 12 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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Expand Up @@ -4006,3 +4006,15 @@ unsigned RISCV::getRVVMCOpcode(unsigned RVVPseudoOpcode) {
return 0;
return RVV->BaseInstr;
}

unsigned RISCV::getDestLog2EEW(const MCInstrDesc &Desc, unsigned Log2SEW) {
unsigned DestEEW =
(Desc.TSFlags & RISCVII::DestEEWMask) >> RISCVII::DestEEWShift;
// EEW = 1
if (DestEEW == 0)
return 0;
// EEW = SEW * n
unsigned Scaled = Log2SEW + (DestEEW - 1);
assert(Scaled >= 3 && Scaled <= 6);
return Scaled;
}
4 changes: 4 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.h
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Expand Up @@ -354,6 +354,10 @@ std::optional<unsigned> getVectorLowDemandedScalarBits(uint16_t Opcode,
// Returns the MC opcode of RVV pseudo instruction.
unsigned getRVVMCOpcode(unsigned RVVPseudoOpcode);

// For a (non-pseudo) RVV instruction \p Desc and the given \p Log2SEW, returns
// the log2 EEW of the destination operand.
unsigned getDestLog2EEW(const MCInstrDesc &Desc, unsigned Log2SEW);

// Special immediate for AVL operand of V pseudo instructions to indicate VLMax.
static constexpr int64_t VLMaxSentinel = -1LL;

Expand Down
57 changes: 32 additions & 25 deletions llvm/lib/Target/RISCV/RISCVInstrInfoV.td
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Expand Up @@ -1104,7 +1104,7 @@ def : InstAlias<"vneg.v $vd, $vs", (VRSUB_VX VR:$vd, VR:$vs, X0, zero_reg)>;
// The destination vector register group cannot overlap a source vector
// register group of a different element width (including the mask register
// if masked), otherwise an illegal instruction exception is raised.
let Constraints = "@earlyclobber $vd" in {
let Constraints = "@earlyclobber $vd", DestEEW = EEWSEWx2 in {
let RVVConstraint = WidenV in {
defm VWADDU_V : VALU_MV_V_X<"vwaddu", 0b110000, "v">;
defm VWSUBU_V : VALU_MV_V_X<"vwsubu", 0b110010, "v">;
Expand All @@ -1121,7 +1121,7 @@ defm VWSUBU_W : VALU_MV_V_X<"vwsubu", 0b110110, "w">;
defm VWADD_W : VALU_MV_V_X<"vwadd", 0b110101, "w">;
defm VWSUB_W : VALU_MV_V_X<"vwsub", 0b110111, "w">;
} // RVVConstraint = WidenW
} // Constraints = "@earlyclobber $vd"
} // Constraints = "@earlyclobber $vd", DestEEW = EEWSEWx2

def : InstAlias<"vwcvt.x.x.v $vd, $vs$vm",
(VWADD_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>;
Expand All @@ -1147,10 +1147,11 @@ defm VMADC_V : VALUm_IV_V_X_I<"vmadc", 0b010001>;
defm VMADC_V : VALUNoVm_IV_V_X_I<"vmadc", 0b010001>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint
defm VSBC_V : VALUm_IV_V_X<"vsbc", 0b010010>;
let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in {
let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint,
DestEEW = EEW1 in {
defm VMSBC_V : VALUm_IV_V_X<"vmsbc", 0b010011>;
defm VMSBC_V : VALUNoVm_IV_V_X<"vmsbc", 0b010011>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint
} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint, DestEEW = EEW1

// Vector Bitwise Logical Instructions
defm VAND_V : VALU_IV_V_X_I<"vand", 0b001001>;
Expand Down Expand Up @@ -1183,7 +1184,7 @@ def : InstAlias<"vncvt.x.x.w $vd, $vs",
(VNSRL_WX VR:$vd, VR:$vs, X0, zero_reg)>;

// Vector Integer Comparison Instructions
let RVVConstraint = NoConstraint in {
let RVVConstraint = NoConstraint, DestEEW = EEW1 in {
defm VMSEQ_V : VCMP_IV_V_X_I<"vmseq", 0b011000>;
defm VMSNE_V : VCMP_IV_V_X_I<"vmsne", 0b011001>;
defm VMSLTU_V : VCMP_IV_V_X<"vmsltu", 0b011010>;
Expand All @@ -1192,7 +1193,7 @@ defm VMSLEU_V : VCMP_IV_V_X_I<"vmsleu", 0b011100>;
defm VMSLE_V : VCMP_IV_V_X_I<"vmsle", 0b011101>;
defm VMSGTU_V : VCMP_IV_X_I<"vmsgtu", 0b011110>;
defm VMSGT_V : VCMP_IV_X_I<"vmsgt", 0b011111>;
} // RVVConstraint = NoConstraint
} // RVVConstraint = NoConstraint, DestEEW = EEW1

def : InstAlias<"vmsgtu.vv $vd, $va, $vb$vm",
(VMSLTU_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>;
Expand All @@ -1204,7 +1205,7 @@ def : InstAlias<"vmsge.vv $vd, $va, $vb$vm",
(VMSLE_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>;

let isCodeGenOnly = 0, isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 0,
mayStore = 0 in {
mayStore = 0, DestEEW = EEW1 in {
// For unsigned comparisons we need to special case 0 immediate to maintain
// the always true/false semantics we would invert if we just decremented the
// immediate like we do for signed. To match the GNU assembler we will use
Expand All @@ -1227,7 +1228,7 @@ def PseudoVMSLT_VI : Pseudo<(outs VR:$vd),
}

let isCodeGenOnly = 0, isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 0,
mayStore = 0 in {
mayStore = 0, DestEEW = EEW1 in {
def PseudoVMSGEU_VX : Pseudo<(outs VR:$vd),
(ins VR:$vs2, GPR:$rs1),
[], "vmsgeu.vx", "$vd, $vs2, $rs1">;
Expand Down Expand Up @@ -1267,11 +1268,12 @@ defm VREMU_V : VDIV_MV_V_X<"vremu", 0b100010>;
defm VREM_V : VDIV_MV_V_X<"vrem", 0b100011>;

// Vector Widening Integer Multiply Instructions
let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in {
let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV,
DestEEW = EEWSEWx2 in {
defm VWMUL_V : VWMUL_MV_V_X<"vwmul", 0b111011>;
defm VWMULU_V : VWMUL_MV_V_X<"vwmulu", 0b111000>;
defm VWMULSU_V : VWMUL_MV_V_X<"vwmulsu", 0b111010>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV
} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV, DestEEW = EEWSEWx2

// Vector Single-Width Integer Multiply-Add Instructions
defm VMACC_V : VMAC_MV_V_X<"vmacc", 0b101101>;
Expand All @@ -1280,10 +1282,12 @@ defm VMADD_V : VMAC_MV_V_X<"vmadd", 0b101001>;
defm VNMSUB_V : VMAC_MV_V_X<"vnmsub", 0b101011>;

// Vector Widening Integer Multiply-Add Instructions
let DestEEW = EEWSEWx2 in {
defm VWMACCU_V : VWMAC_MV_V_X<"vwmaccu", 0b111100>;
defm VWMACC_V : VWMAC_MV_V_X<"vwmacc", 0b111101>;
defm VWMACCSU_V : VWMAC_MV_V_X<"vwmaccsu", 0b111111>;
defm VWMACCUS_V : VWMAC_MV_X<"vwmaccus", 0b111110>;
} // DestEEW = EEWSEWx2

// Vector Integer Merge Instructions
defm VMERGE_V : VMRG_IV_V_X_I<"vmerge", 0b010111>;
Expand Down Expand Up @@ -1342,7 +1346,8 @@ defm VFRSUB_V : VALU_FV_F<"vfrsub", 0b100111>;
// Vector Widening Floating-Point Add/Subtract Instructions
let Constraints = "@earlyclobber $vd",
Uses = [FRM],
mayRaiseFPException = true in {
mayRaiseFPException = true,
DestEEW = EEWSEWx2 in {
let RVVConstraint = WidenV in {
defm VFWADD_V : VWALU_FV_V_F<"vfwadd", 0b110000, "v">;
defm VFWSUB_V : VWALU_FV_V_F<"vfwsub", 0b110010, "v">;
Expand All @@ -1355,7 +1360,7 @@ let RVVConstraint = WidenW in {
defm VFWADD_W : VWALU_FV_V_F<"vfwadd", 0b110100, "w">;
defm VFWSUB_W : VWALU_FV_V_F<"vfwsub", 0b110110, "w">;
} // RVVConstraint = WidenW
} // Constraints = "@earlyclobber $vd", Uses = [FRM], mayRaiseFPException = true
} // Constraints = "@earlyclobber $vd", Uses = [FRM], mayRaiseFPException = true, DestEEW = EEWSEWx2

// Vector Single-Width Floating-Point Multiply/Divide Instructions
let Uses = [FRM], mayRaiseFPException = true in {
Expand All @@ -1366,9 +1371,9 @@ defm VFRDIV_V : VDIV_FV_F<"vfrdiv", 0b100001>;

// Vector Widening Floating-Point Multiply
let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV,
Uses = [FRM], mayRaiseFPException = true in {
Uses = [FRM], mayRaiseFPException = true, DestEEW = EEWSEWx2 in {
defm VFWMUL_V : VWMUL_FV_V_F<"vfwmul", 0b111000>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV, Uses = [FRM], mayRaiseFPException = true
} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV, Uses = [FRM], mayRaiseFPException = true, DestEEW = EEWSEWx2

// Vector Single-Width Floating-Point Fused Multiply-Add Instructions
let Uses = [FRM], mayRaiseFPException = true in {
Expand All @@ -1383,12 +1388,12 @@ defm VFNMSUB_V : VMAC_FV_V_F<"vfnmsub", 0b101011>;
}

// Vector Widening Floating-Point Fused Multiply-Add Instructions
let Uses = [FRM], mayRaiseFPException = true in {
let Uses = [FRM], mayRaiseFPException = true, DestEEW = EEWSEWx2 in {
defm VFWMACC_V : VWMAC_FV_V_F<"vfwmacc", 0b111100>;
defm VFWNMACC_V : VWMAC_FV_V_F<"vfwnmacc", 0b111101>;
defm VFWMSAC_V : VWMAC_FV_V_F<"vfwmsac", 0b111110>;
defm VFWNMSAC_V : VWMAC_FV_V_F<"vfwnmsac", 0b111111>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV, Uses = [FRM], mayRaiseFPException = true
} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV, Uses = [FRM], mayRaiseFPException = true, DestEEW = EEWSEWx2

// Vector Floating-Point Square-Root Instruction
let Uses = [FRM], mayRaiseFPException = true in {
Expand Down Expand Up @@ -1420,14 +1425,14 @@ def : InstAlias<"vfabs.v $vd, $vs",
(VFSGNJX_VV VR:$vd, VR:$vs, VR:$vs, zero_reg)>;

// Vector Floating-Point Compare Instructions
let RVVConstraint = NoConstraint, mayRaiseFPException = true in {
let RVVConstraint = NoConstraint, mayRaiseFPException = true, DestEEW = EEW1 in {
defm VMFEQ_V : VCMP_FV_V_F<"vmfeq", 0b011000>;
defm VMFNE_V : VCMP_FV_V_F<"vmfne", 0b011100>;
defm VMFLT_V : VCMP_FV_V_F<"vmflt", 0b011011>;
defm VMFLE_V : VCMP_FV_V_F<"vmfle", 0b011001>;
defm VMFGT_V : VCMP_FV_F<"vmfgt", 0b011101>;
defm VMFGE_V : VCMP_FV_F<"vmfge", 0b011111>;
} // RVVConstraint = NoConstraint, mayRaiseFPException = true
} // RVVConstraint = NoConstraint, mayRaiseFPException = true, DestEEW = EEW1

def : InstAlias<"vmfgt.vv $vd, $va, $vb$vm",
(VMFLT_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>;
Expand Down Expand Up @@ -1471,7 +1476,7 @@ defm VFCVT_F_X_V : VCVTF_IV_VS2<"vfcvt.f.x.v", 0b010010, 0b00011>;

// Widening Floating-Point/Integer Type-Convert Instructions
let Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt,
mayRaiseFPException = true in {
mayRaiseFPException = true, DestEEW = EEWSEWx2 in {
let Uses = [FRM] in {
defm VFWCVT_XU_F_V : VWCVTI_FV_VS2<"vfwcvt.xu.f.v", 0b010010, 0b01000>;
defm VFWCVT_X_F_V : VWCVTI_FV_VS2<"vfwcvt.x.f.v", 0b010010, 0b01001>;
Expand All @@ -1481,7 +1486,7 @@ defm VFWCVT_RTZ_X_F_V : VWCVTI_FV_VS2<"vfwcvt.rtz.x.f.v", 0b010010, 0b01111>;
defm VFWCVT_F_XU_V : VWCVTF_IV_VS2<"vfwcvt.f.xu.v", 0b010010, 0b01010>;
defm VFWCVT_F_X_V : VWCVTF_IV_VS2<"vfwcvt.f.x.v", 0b010010, 0b01011>;
defm VFWCVT_F_F_V : VWCVTF_FV_VS2<"vfwcvt.f.f.v", 0b010010, 0b01100>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt
} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt, DestEEW = EEWSEWx2

// Narrowing Floating-Point/Integer Type-Convert Instructions
let Constraints = "@earlyclobber $vd", mayRaiseFPException = true in {
Expand Down Expand Up @@ -1515,14 +1520,14 @@ defm VREDXOR : VRED_MV_V<"vredxor", 0b000011>;
} // RVVConstraint = NoConstraint, ElementsDependOn = EltDepsVLMask

// Vector Widening Integer Reduction Instructions
let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint, ElementsDependOn = EltDepsVLMask in {
let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint, ElementsDependOn = EltDepsVLMask, DestEEW = EEWSEWx2 in {
// Set earlyclobber for following instructions for second and mask operands.
// This has the downside that the earlyclobber constraint is too coarse and
// will impose unnecessary restrictions by not allowing the destination to
// overlap with the first (wide) operand.
defm VWREDSUMU : VWRED_IV_V<"vwredsumu", 0b110000>;
defm VWREDSUM : VWRED_IV_V<"vwredsum", 0b110001>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint, ElementsDependOn = EltDepsVLMask
} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint, ElementsDependOn = EltDepsVLMask, DestEEW = EEWSEWx2

} // Predicates = [HasVInstructions]

Expand All @@ -1543,7 +1548,7 @@ def : InstAlias<"vfredsum.vs $vd, $vs2, $vs1$vm",
(VFREDUSUM_VS VR:$vd, VR:$vs2, VR:$vs1, VMaskOp:$vm), 0>;

// Vector Widening Floating-Point Reduction Instructions
let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint, ElementsDependOn = EltDepsVLMask in {
let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint, ElementsDependOn = EltDepsVLMask, DestEEW = EEWSEWx2 in {
// Set earlyclobber for following instructions for second and mask operands.
// This has the downside that the earlyclobber constraint is too coarse and
// will impose unnecessary restrictions by not allowing the destination to
Expand All @@ -1552,15 +1557,15 @@ let Uses = [FRM], mayRaiseFPException = true in {
defm VFWREDOSUM : VWREDO_FV_V<"vfwredosum", 0b110011>;
defm VFWREDUSUM : VWRED_FV_V<"vfwredusum", 0b110001>;
}
} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint, ElementsDependOn = EltDepsVLMask
} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint, ElementsDependOn = EltDepsVLMask, DestEEW = EEWSEWx2

def : InstAlias<"vfwredsum.vs $vd, $vs2, $vs1$vm",
(VFWREDUSUM_VS VR:$vd, VR:$vs2, VR:$vs1, VMaskOp:$vm), 0>;
} // Predicates = [HasVInstructionsAnyF]

let Predicates = [HasVInstructions] in {
// Vector Mask-Register Logical Instructions
let RVVConstraint = NoConstraint in {
let RVVConstraint = NoConstraint, DestEEW = EEW1 in {
defm VMAND_M : VMALU_MV_Mask<"vmand", 0b011001, "m">;
defm VMNAND_M : VMALU_MV_Mask<"vmnand", 0b011101, "m">;
defm VMANDN_M : VMALU_MV_Mask<"vmandn", 0b011000, "m">;
Expand Down Expand Up @@ -1607,12 +1612,14 @@ def : InstAlias<"vpopc.m $vd, $vs2$vm",

let Constraints = "@earlyclobber $vd", RVVConstraint = Iota, ElementsDependOn = EltDepsVLMask in {

let DestEEW = EEW1 in {
// vmsbf.m set-before-first mask bit
defm VMSBF_M : VMSFS_MV_V<"vmsbf.m", 0b010100, 0b00001>;
// vmsif.m set-including-first mask bit
defm VMSIF_M : VMSFS_MV_V<"vmsif.m", 0b010100, 0b00011>;
// vmsof.m set-only-first mask bit
defm VMSOF_M : VMSFS_MV_V<"vmsof.m", 0b010100, 0b00010>;
} // DestEEW = EEW1
// Vector Iota Instruction
defm VIOTA_M : VIOTA_MV_V<"viota.m", 0b010100, 0b10000>;

Expand Down
9 changes: 6 additions & 3 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
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Expand Up @@ -201,21 +201,24 @@ let Predicates = [HasVendorXSfvcp], mayLoad = 0, mayStore = 0,
defm FVW : CustomSiFiveVCIX<"fvw", VCIX_XVW, VR, VR, FPR32>, Sched<[]>;
}

let Predicates = [HasVendorXSfvqmaccdod], DecoderNamespace = "XSfvqmaccdod" in {
let Predicates = [HasVendorXSfvqmaccdod], DecoderNamespace = "XSfvqmaccdod",
DestEEW = EEWSEWx4 in {
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Do we need to know that the input EMUL and output EMUL are the same for these even though the element width changes?

def VQMACCU_2x8x2 : CustomSiFiveVMACC<0b101100, OPMVV, "sf.vqmaccu.2x8x2">;
def VQMACC_2x8x2 : CustomSiFiveVMACC<0b101101, OPMVV, "sf.vqmacc.2x8x2">;
def VQMACCUS_2x8x2 : CustomSiFiveVMACC<0b101110, OPMVV, "sf.vqmaccus.2x8x2">;
def VQMACCSU_2x8x2 : CustomSiFiveVMACC<0b101111, OPMVV, "sf.vqmaccsu.2x8x2">;
}

let Predicates = [HasVendorXSfvqmaccqoq], DecoderNamespace = "XSfvqmaccqoq" in {
let Predicates = [HasVendorXSfvqmaccqoq], DecoderNamespace = "XSfvqmaccqoq",
DestEEW = EEWSEWx4 in {
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Do we need to know that the output EMUL increases by a factor of 2, but the element size increases by a factor of 4?

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Given what @preames has said, I don't think we need the EMULs to match.

For tryToReduceVL, we replace the source's VL with a smaller VL, which gives the same result regardless of the source's EMUL.

For foldVMV_V_V, we replace a vmv.v.v with a source with the same EEW and a less than or equal VL.

At EMUL >= m1, the EMULs will match because the register classes will need to match.

We might have mismatched EMULs when < m1, but even if we increase or decrease the resulting LMUL the result is the same:

%add:vr = PseudoVADD_VV_MF8 %pt, %1, %2, 2/*VL*/, 4 /*SEW*/, 0
%vmv:vr = PseudoVMV_V_V_MF4 %pt, %add, 3/*VL*/, 4 /*SEW*/, 0
->
%vmv:vr = PseudoVADD_VV_MF8 %pt, %1, %2, 2 /*VL*/, 4 /*SEW*/, 0

%add:vr = PseudoVADD_VV_MF4 %pt, %1, %2, 2/*VL*/, 4 /*SEW*/, 0
%vmv:vr = PseudoVMV_V_V_MF8 %pt, %add, 3/*VL*/, 4 /*SEW*/, 0
->
%vmv:vr = PseudoVADD_VV_MF4 %pt, %1, %2, 2 /*VL*/, 4 /*SEW*/, 0

Because the specification mandates that the tail includes the entire vector register.

When LMUL < 1, the tail includes the elements past VLMAX that are held in the same vector register.

def VQMACCU_4x8x4 : CustomSiFiveVMACC<0b111100, OPMVV, "sf.vqmaccu.4x8x4">;
def VQMACC_4x8x4 : CustomSiFiveVMACC<0b111101, OPMVV, "sf.vqmacc.4x8x4">;
def VQMACCUS_4x8x4 : CustomSiFiveVMACC<0b111110, OPMVV, "sf.vqmaccus.4x8x4">;
def VQMACCSU_4x8x4 : CustomSiFiveVMACC<0b111111, OPMVV, "sf.vqmaccsu.4x8x4">;
}

let Predicates = [HasVendorXSfvfwmaccqqq], DecoderNamespace = "XSfvfwmaccqqq" in {
let Predicates = [HasVendorXSfvfwmaccqqq], DecoderNamespace = "XSfvfwmaccqqq",
DestEEW = EEWSEWx2 in {
def VFWMACC_4x4x4 : CustomSiFiveVMACC<0b111100, OPFVV, "sf.vfwmacc.4x4x4">;
}

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5 changes: 3 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
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Original file line number Diff line number Diff line change
Expand Up @@ -19,14 +19,15 @@

let Predicates = [HasStdExtZvfbfmin], Constraints = "@earlyclobber $vd",
mayRaiseFPException = true in {
let RVVConstraint = WidenCvt in
let RVVConstraint = WidenCvt, DestEEW = EEWSEWx2 in
defm VFWCVTBF16_F_F_V : VWCVTF_FV_VS2<"vfwcvtbf16.f.f.v", 0b010010, 0b01101>;
let Uses = [FRM] in
defm VFNCVTBF16_F_F_W : VNCVTF_FV_VS2<"vfncvtbf16.f.f.w", 0b010010, 0b11101>;
}

let Predicates = [HasStdExtZvfbfwma],
Constraints = "@earlyclobber $vd_wb, $vd = $vd_wb",
RVVConstraint = WidenV, Uses = [FRM], mayRaiseFPException = true in {
RVVConstraint = WidenV, Uses = [FRM], mayRaiseFPException = true,
DestEEW = EEWSEWx2 in {
defm VFWMACCBF16_V : VWMAC_FV_V_F<"vfwmaccbf16", 0b111011>;
}
3 changes: 2 additions & 1 deletion llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
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Expand Up @@ -123,7 +123,8 @@ let Predicates = [HasStdExtZvbb] in {
def VCLZ_V : VALUVs2<0b010010, 0b01100, OPMVV, "vclz.v">;
def VCPOP_V : VALUVs2<0b010010, 0b01110, OPMVV, "vcpop.v">;
def VCTZ_V : VALUVs2<0b010010, 0b01101, OPMVV, "vctz.v">;
let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in
let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV,
DestEEW = EEWSEWx2 in
defm VWSLL_V : VSHT_IV_V_X_I<"vwsll", 0b110101>;
} // Predicates = [HasStdExtZvbb]

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