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[AMDGPU] Use range-based for loops (NFC) #106184

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Merged
merged 1 commit into from
Aug 27, 2024
Merged

[AMDGPU] Use range-based for loops (NFC) #106184

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11 changes: 4 additions & 7 deletions llvm/lib/Target/AMDGPU/R600EmitClauseMarkers.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -180,11 +180,8 @@ class R600EmitClauseMarkers : public MachineFunctionPass {
MachineBasicBlock::iterator BBEnd) {
const R600RegisterInfo &TRI = TII->getRegisterInfo();
//TODO: change this to defs?
for (MachineInstr::const_mop_iterator
MOI = Def->operands_begin(),
MOE = Def->operands_end(); MOI != MOE; ++MOI) {
if (!MOI->isReg() || !MOI->isDef() ||
TRI.isPhysRegLiveAcrossClauses(MOI->getReg()))
for (MachineOperand &MO : Def->all_defs()) {
if (TRI.isPhysRegLiveAcrossClauses(MO.getReg()))
continue;

// Def defines a clause local register, so check that its use will fit
Expand All @@ -208,11 +205,11 @@ class R600EmitClauseMarkers : public MachineFunctionPass {
// occur in the same basic block as its definition, because
// it is illegal for the scheduler to schedule them in
// different blocks.
if (UseI->readsRegister(MOI->getReg(), &TRI))
if (UseI->readsRegister(MO.getReg(), &TRI))
LastUseCount = AluInstCount;

// Exit early if the current use kills the register
if (UseI != Def && UseI->killsRegister(MOI->getReg(), &TRI))
if (UseI != Def && UseI->killsRegister(MO.getReg(), &TRI))
break;
}
if (LastUseCount)
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8 changes: 2 additions & 6 deletions llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp
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Expand Up @@ -350,13 +350,9 @@ void R600SchedStrategy::AssignSlot(MachineInstr* MI, unsigned Slot) {
Register DestReg = MI->getOperand(DstIndex).getReg();
// PressureRegister crashes if an operand is def and used in the same inst
// and we try to constraint its regclass
for (MachineInstr::mop_iterator It = MI->operands_begin(),
E = MI->operands_end(); It != E; ++It) {
MachineOperand &MO = *It;
if (MO.isReg() && !MO.isDef() &&
MO.getReg() == DestReg)
for (const MachineOperand &MO : MI->all_uses())
if (MO.getReg() == DestReg)
return;
}
// Constrains the regclass of DestReg to assign it to Slot
switch (Slot) {
case 0:
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6 changes: 2 additions & 4 deletions llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
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Expand Up @@ -883,10 +883,8 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
// can be used as the actual source after export patching, so
// we need to treat them like sources and set the EXP_CNT
// score.
for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) {
MachineOperand &DefMO = Inst.getOperand(I);
if (DefMO.isReg() && DefMO.isDef() &&
TRI->isVGPR(*MRI, DefMO.getReg())) {
for (MachineOperand &DefMO : Inst.all_defs()) {
if (TRI->isVGPR(*MRI, DefMO.getReg())) {
setRegScore(
TRI->getEncodingValue(AMDGPU::getMCReg(DefMO.getReg(), *ST)),
EXP_CNT, CurrScore);
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