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[AArch64] Fix sched model of Neoverse N2 #106376

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Merged
merged 1 commit into from
Sep 18, 2024
Merged

[AArch64] Fix sched model of Neoverse N2 #106376

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9 changes: 5 additions & 4 deletions llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
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Original file line number Diff line number Diff line change
Expand Up @@ -836,9 +836,11 @@ def : InstRW<[N2Write_3c_1V], (instregex "^FCVT[AMNPZ][SU][SU][WX][HSD]r$")>;
def : SchedAlias<WriteFCvt, N2Write_3c_1V0>;

// FP move, immed
// FP move, register
def : SchedAlias<WriteFImm, N2Write_2c_1V>;

// FP move, register
def : InstRW<[N2Write_2c_1V], (instrs FMOVHr, FMOVSr, FMOVDr)>;

// FP transfer, from gen to low half of vec reg
def : InstRW<[N2Write_3c_1M0], (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr,
FMOVHWr, FMOVHXr, FMOVSWr, FMOVDXr)>;
Expand All @@ -858,9 +860,8 @@ def : InstRW<[N2Write_6c_1L], (instregex "^LDR[SDQ]l$",
"^LDUR[BHSDQ]i$")>;

// Load vector reg, immed post-index
def : InstRW<[N2Write_6c_1I_1L, WriteI], (instregex "^LDR[BHSDQ]post$")>;
// Load vector reg, immed pre-index
def : InstRW<[WriteAdr, N2Write_6c_1I_1L], (instregex "^LDR[BHSDQ]pre$")>;
def : InstRW<[WriteAdr, N2Write_6c_1I_1L], (instregex "^LDR[BHSDQ](post|pre)$")>;

// Load vector reg, unsigned immed
def : InstRW<[N2Write_6c_1L], (instregex "^LDR[BHSDQ]ui$")>;
Expand Down Expand Up @@ -1119,7 +1120,7 @@ def : InstRW<[N2Write_5c_1V], (instregex "^FMLALv", "^FMLSLv")>;
// ASIMD FP round, D-form F32 and Q-form F64
def : InstRW<[N2Write_3c_1V0],
(instregex "^FRINT[AIMNPXZ]v2f(32|64)$",
"^FRINT[32|64)[XZ]v2f(32|64)$")>;
"^FRINT(32|64)[XZ]v2f(32|64)$")>;

// ASIMD FP round, D-form F16 and Q-form F32
def : InstRW<[N2Write_4c_2V0],
Expand Down
50 changes: 25 additions & 25 deletions llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-writeback.s
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Original file line number Diff line number Diff line change
Expand Up @@ -3298,28 +3298,28 @@ add x0, x27, 1

# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 1000
# CHECK-NEXT: Total Cycles: 3004
# CHECK-NEXT: Total Cycles: 508
# CHECK-NEXT: Total uOps: 2000

# CHECK: Dispatch Width: 10
# CHECK-NEXT: uOps Per Cycle: 0.67
# CHECK-NEXT: IPC: 0.33
# CHECK-NEXT: uOps Per Cycle: 3.94
# CHECK-NEXT: IPC: 1.97
# CHECK-NEXT: Block RThroughput: 3.8

# CHECK: Timeline view:
# CHECK-NEXT: 0123456789 0123
# CHECK-NEXT: Index 0123456789 0123456789
# CHECK-NEXT: 012
# CHECK-NEXT: Index 0123456789

# CHECK: [0,0] DeeeeeeER . . . . . . ldr b1, [x27], #254
# CHECK-NEXT: [0,1] D======eER. . . . . . add x0, x27, #1
# CHECK-NEXT: [0,2] D======eeeeeeER. . . . . ldr h1, [x27], #254
# CHECK-NEXT: [0,3] D============eER . . . . add x0, x27, #1
# CHECK-NEXT: [0,4] .D===========eeeeeeER . . . ldr s1, [x27], #254
# CHECK-NEXT: [0,5] .D=================eER . . . add x0, x27, #1
# CHECK-NEXT: [0,6] .D=================eeeeeeER . . ldr d1, [x27], #254
# CHECK-NEXT: [0,7] .D=======================eER . . add x0, x27, #1
# CHECK-NEXT: [0,8] . D======================eeeeeeER. ldr q1, [x27], #254
# CHECK-NEXT: [0,9] . D============================eER add x0, x27, #1
# CHECK: [0,0] DeeeeeeER . . ldr b1, [x27], #254
# CHECK-NEXT: [0,1] D=eE----R . . add x0, x27, #1
# CHECK-NEXT: [0,2] D=eeeeeeER. . ldr h1, [x27], #254
# CHECK-NEXT: [0,3] D==eE----R. . add x0, x27, #1
# CHECK-NEXT: [0,4] .D=eeeeeeER . ldr s1, [x27], #254
# CHECK-NEXT: [0,5] .D==eE----R . add x0, x27, #1
# CHECK-NEXT: [0,6] .D==eeeeeeER. ldr d1, [x27], #254
# CHECK-NEXT: [0,7] .D===eE----R. add x0, x27, #1
# CHECK-NEXT: [0,8] . D==eeeeeeER ldr q1, [x27], #254
# CHECK-NEXT: [0,9] . D===eE----R add x0, x27, #1

# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
Expand All @@ -3329,16 +3329,16 @@ add x0, x27, 1

# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ldr b1, [x27], #254
# CHECK-NEXT: 1. 1 7.0 0.0 0.0 add x0, x27, #1
# CHECK-NEXT: 2. 1 7.0 0.0 0.0 ldr h1, [x27], #254
# CHECK-NEXT: 3. 1 13.0 0.0 0.0 add x0, x27, #1
# CHECK-NEXT: 4. 1 12.0 0.0 0.0 ldr s1, [x27], #254
# CHECK-NEXT: 5. 1 18.0 0.0 0.0 add x0, x27, #1
# CHECK-NEXT: 6. 1 18.0 0.0 0.0 ldr d1, [x27], #254
# CHECK-NEXT: 7. 1 24.0 0.0 0.0 add x0, x27, #1
# CHECK-NEXT: 8. 1 23.0 0.0 0.0 ldr q1, [x27], #254
# CHECK-NEXT: 9. 1 29.0 0.0 0.0 add x0, x27, #1
# CHECK-NEXT: 1 15.2 0.1 0.0 <total>
# CHECK-NEXT: 1. 1 2.0 0.0 4.0 add x0, x27, #1
# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ldr h1, [x27], #254
# CHECK-NEXT: 3. 1 3.0 0.0 4.0 add x0, x27, #1
# CHECK-NEXT: 4. 1 2.0 0.0 0.0 ldr s1, [x27], #254
# CHECK-NEXT: 5. 1 3.0 0.0 4.0 add x0, x27, #1
# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ldr d1, [x27], #254
# CHECK-NEXT: 7. 1 4.0 0.0 4.0 add x0, x27, #1
# CHECK-NEXT: 8. 1 3.0 0.0 0.0 ldr q1, [x27], #254
# CHECK-NEXT: 9. 1 4.0 0.0 4.0 add x0, x27, #1
# CHECK-NEXT: 1 2.7 0.1 2.0 <total>

# CHECK: [47] Code Region - G48

Expand Down
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