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[DAG] Prefer 0.0 over -0.0 as neutral value for FADD w/NoSignedZero #106616

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Aug 30, 2024
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4 changes: 3 additions & 1 deletion llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -13267,7 +13267,9 @@ SDValue SelectionDAG::getNeutralElement(unsigned Opcode, const SDLoc &DL,
case ISD::SMIN:
return getConstant(APInt::getSignedMaxValue(VT.getSizeInBits()), DL, VT);
case ISD::FADD:
return getConstantFP(-0.0, DL, VT);
// If flags allow, prefer positive zero single it's generally cheaper
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Weird typo "single" for "since"?

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Fixed in e1bde1c

// to materialize on most targets.
return getConstantFP(Flags.hasNoSignedZeros() ? 0.0 : -0.0, DL, VT);
case ISD::FMUL:
return getConstantFP(1.0, DL, VT);
case ISD::FMINNUM:
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3 changes: 1 addition & 2 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
Original file line number Diff line number Diff line change
Expand Up @@ -524,8 +524,7 @@ define float @vreduce_fadd_v7f32_neutralstart_fast(ptr %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vmv.s.x v10, zero
; CHECK-NEXT: vfredusum.vs v8, v8, v10
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
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