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[LegalizeVectorOps] Defer UnrollVectorOp in ExpandFNEG to caller. #106783

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Merged
merged 1 commit into from
Sep 2, 2024
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[LegalizeVectorOps] Defer UnrollVectorOp in ExpandFNEG to caller. #106783

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27 changes: 15 additions & 12 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -937,8 +937,11 @@ void VectorLegalizer::Expand(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
ExpandUINT_TO_FLOAT(Node, Results);
return;
case ISD::FNEG:
Results.push_back(ExpandFNEG(Node));
return;
if (SDValue Expanded = ExpandFNEG(Node)) {
Results.push_back(Expanded);
return;
}
break;
case ISD::FSUB:
ExpandFSUB(Node, Results);
return;
Expand Down Expand Up @@ -1773,16 +1776,16 @@ SDValue VectorLegalizer::ExpandFNEG(SDNode *Node) {
EVT IntVT = VT.changeVectorElementTypeToInteger();

// FIXME: The FSUB check is here to force unrolling v1f64 vectors on AArch64.
if (TLI.isOperationLegalOrCustom(ISD::XOR, IntVT) &&
TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) {
SDLoc DL(Node);
SDValue Cast = DAG.getNode(ISD::BITCAST, DL, IntVT, Node->getOperand(0));
SDValue SignMask = DAG.getConstant(
APInt::getSignMask(IntVT.getScalarSizeInBits()), DL, IntVT);
SDValue Xor = DAG.getNode(ISD::XOR, DL, IntVT, Cast, SignMask);
return DAG.getNode(ISD::BITCAST, DL, VT, Xor);
}
return DAG.UnrollVectorOp(Node);
if (!TLI.isOperationLegalOrCustom(ISD::XOR, IntVT) ||
!TLI.isOperationLegalOrCustom(ISD::FSUB, VT))
return SDValue();

SDLoc DL(Node);
SDValue Cast = DAG.getNode(ISD::BITCAST, DL, IntVT, Node->getOperand(0));
SDValue SignMask = DAG.getConstant(
APInt::getSignMask(IntVT.getScalarSizeInBits()), DL, IntVT);
SDValue Xor = DAG.getNode(ISD::XOR, DL, IntVT, Cast, SignMask);
return DAG.getNode(ISD::BITCAST, DL, VT, Xor);
}

void VectorLegalizer::ExpandFSUB(SDNode *Node,
Expand Down
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