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[RISCV] Use RNE rounding mode for fcvt.s.bf16. Don't print the rounding mode if RNE. #106948

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Merged
merged 2 commits into from
Sep 3, 2024
Merged

[RISCV] Use RNE rounding mode for fcvt.s.bf16. Don't print the rounding mode if RNE. #106948

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90aa61e
[RISCV] Use RNE rounding mode for fcvt.s.bf16. Don't print the roundi…
topperc Sep 2, 2024
6fedd16
Merge remote-tracking branch 'origin/main' into pr/rne-bf16
topperc Sep 3, 2024
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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ def riscv_fpround_bf16
let Predicates = [HasStdExtZfbfmin] in {
def FCVT_BF16_S : FPUnaryOp_r_frm<0b0100010, 0b01000, FPR16, FPR32, "fcvt.bf16.s">,
Sched<[WriteFCvtF32ToF16, ReadFCvtF32ToF16]>;
def FCVT_S_BF16 : FPUnaryOp_r_frm<0b0100000, 0b00110, FPR32, FPR16, "fcvt.s.bf16">,
def FCVT_S_BF16 : FPUnaryOp_r_frmlegacy<0b0100000, 0b00110, FPR32, FPR16, "fcvt.s.bf16">,
Sched<[WriteFCvtF16ToF32, ReadFCvtF16ToF32]>;
} // Predicates = [HasStdExtZfbfmin]

Expand All @@ -50,7 +50,7 @@ def : StPat<store, FSH, FPR16, bf16>;
def : Pat<(bf16 (riscv_fpround_bf16 FPR32:$rs1)),
(FCVT_BF16_S FPR32:$rs1, FRM_DYN)>;
def : Pat<(fpextend (bf16 FPR16:$rs1)),
(FCVT_S_BF16 FPR16:$rs1, FRM_DYN)>;
(FCVT_S_BF16 FPR16:$rs1, FRM_RNE)>;

// Moves (no conversion)
def : Pat<(bf16 (riscv_fmv_h_x GPR:$src)), (FMV_H_X GPR:$src)>;
Expand Down
26 changes: 13 additions & 13 deletions llvm/test/CodeGen/RISCV/bfloat-convert.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@
define i16 @fcvt_si_bf16(bfloat %a) nounwind {
; CHECK32ZFBFMIN-LABEL: fcvt_si_bf16:
; CHECK32ZFBFMIN: # %bb.0:
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK32ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
; CHECK32ZFBFMIN-NEXT: ret
;
Expand All @@ -32,7 +32,7 @@ define i16 @fcvt_si_bf16(bfloat %a) nounwind {
;
; CHECK64ZFBFMIN-LABEL: fcvt_si_bf16:
; CHECK64ZFBFMIN: # %bb.0:
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK64ZFBFMIN-NEXT: fcvt.l.s a0, fa5, rtz
; CHECK64ZFBFMIN-NEXT: ret
;
Expand Down Expand Up @@ -120,7 +120,7 @@ declare i16 @llvm.fptosi.sat.i16.bf16(bfloat)
define i16 @fcvt_ui_bf16(bfloat %a) nounwind {
; CHECK32ZFBFMIN-LABEL: fcvt_ui_bf16:
; CHECK32ZFBFMIN: # %bb.0:
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
; CHECK32ZFBFMIN-NEXT: ret
;
Expand All @@ -134,7 +134,7 @@ define i16 @fcvt_ui_bf16(bfloat %a) nounwind {
;
; CHECK64ZFBFMIN-LABEL: fcvt_ui_bf16:
; CHECK64ZFBFMIN: # %bb.0:
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK64ZFBFMIN-NEXT: fcvt.lu.s a0, fa5, rtz
; CHECK64ZFBFMIN-NEXT: ret
;
Expand Down Expand Up @@ -206,7 +206,7 @@ declare i16 @llvm.fptoui.sat.i16.bf16(bfloat)
define i32 @fcvt_w_bf16(bfloat %a) nounwind {
; CHECK32ZFBFMIN-LABEL: fcvt_w_bf16:
; CHECK32ZFBFMIN: # %bb.0:
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK32ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
; CHECK32ZFBFMIN-NEXT: ret
;
Expand Down Expand Up @@ -288,7 +288,7 @@ declare i32 @llvm.fptosi.sat.i32.bf16(bfloat)
define i32 @fcvt_wu_bf16(bfloat %a) nounwind {
; CHECK32ZFBFMIN-LABEL: fcvt_wu_bf16:
; CHECK32ZFBFMIN: # %bb.0:
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
; CHECK32ZFBFMIN-NEXT: ret
;
Expand Down Expand Up @@ -320,7 +320,7 @@ define i32 @fcvt_wu_bf16(bfloat %a) nounwind {
define i32 @fcvt_wu_bf16_multiple_use(bfloat %x, ptr %y) nounwind {
; CHECK32ZFBFMIN-LABEL: fcvt_wu_bf16_multiple_use:
; CHECK32ZFBFMIN: # %bb.0:
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
; CHECK32ZFBFMIN-NEXT: seqz a1, a0
; CHECK32ZFBFMIN-NEXT: add a0, a0, a1
Expand Down Expand Up @@ -438,7 +438,7 @@ define i64 @fcvt_l_bf16(bfloat %a) nounwind {
;
; CHECK64ZFBFMIN-LABEL: fcvt_l_bf16:
; CHECK64ZFBFMIN: # %bb.0:
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK64ZFBFMIN-NEXT: fcvt.l.s a0, fa5, rtz
; CHECK64ZFBFMIN-NEXT: ret
;
Expand Down Expand Up @@ -625,7 +625,7 @@ define i64 @fcvt_lu_bf16(bfloat %a) nounwind {
;
; CHECK64ZFBFMIN-LABEL: fcvt_lu_bf16:
; CHECK64ZFBFMIN: # %bb.0:
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK64ZFBFMIN-NEXT: fcvt.lu.s a0, fa5, rtz
; CHECK64ZFBFMIN-NEXT: ret
;
Expand Down Expand Up @@ -1470,7 +1470,7 @@ define signext i32 @fcvt_bf16_wu_demanded_bits(i32 signext %0, ptr %1) nounwind
define signext i8 @fcvt_w_s_i8(bfloat %a) nounwind {
; CHECK32ZFBFMIN-LABEL: fcvt_w_s_i8:
; CHECK32ZFBFMIN: # %bb.0:
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK32ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
; CHECK32ZFBFMIN-NEXT: ret
;
Expand All @@ -1484,7 +1484,7 @@ define signext i8 @fcvt_w_s_i8(bfloat %a) nounwind {
;
; CHECK64ZFBFMIN-LABEL: fcvt_w_s_i8:
; CHECK64ZFBFMIN: # %bb.0:
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK64ZFBFMIN-NEXT: fcvt.l.s a0, fa5, rtz
; CHECK64ZFBFMIN-NEXT: ret
;
Expand Down Expand Up @@ -1572,7 +1572,7 @@ declare i8 @llvm.fptosi.sat.i8.bf16(bfloat)
define zeroext i8 @fcvt_wu_s_i8(bfloat %a) nounwind {
; CHECK32ZFBFMIN-LABEL: fcvt_wu_s_i8:
; CHECK32ZFBFMIN: # %bb.0:
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
; CHECK32ZFBFMIN-NEXT: ret
;
Expand All @@ -1586,7 +1586,7 @@ define zeroext i8 @fcvt_wu_s_i8(bfloat %a) nounwind {
;
; CHECK64ZFBFMIN-LABEL: fcvt_wu_s_i8:
; CHECK64ZFBFMIN: # %bb.0:
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK64ZFBFMIN-NEXT: fcvt.lu.s a0, fa5, rtz
; CHECK64ZFBFMIN-NEXT: ret
;
Expand Down
5 changes: 4 additions & 1 deletion llvm/test/MC/RISCV/fp-default-rounding-mode.s
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Expand Up @@ -193,9 +193,12 @@ fcvt.h.lu fa0, a0

# Zfbfmin instructions

# CHECK-INST: fcvt.s.bf16 fa0, fa0, dyn{{$}}
# CHECK-INST: fcvt.s.bf16 fa0, fa0{{$}}
# CHECK-ALIAS: fcvt.s.bf16 fa0, fa0{{$}}
fcvt.s.bf16 fa0, fa0
# CHECK-INST: fcvt.s.bf16 fa0, fa0{{$}}
# CHECK-ALIAS: fcvt.s.bf16 fa0, fa0{{$}}
fcvt.s.bf16 fa0, fa0, rne

# CHECK-INST: fcvt.bf16.s fa0, fa0, dyn{{$}}
# CHECK-ALIAS: fcvt.bf16.s fa0, fa0{{$}}
Expand Down
5 changes: 4 additions & 1 deletion llvm/test/MC/RISCV/rv32zfbfmin-valid.s
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Expand Up @@ -49,8 +49,11 @@ fmv.x.h a2, fs7
fmv.h.x ft1, a6

# CHECK-ASM-AND-OBJ: fcvt.s.bf16 fa0, ft0
# CHECK-ASM: encoding: [0x53,0x75,0x60,0x40]
# CHECK-ASM: encoding: [0x53,0x05,0x60,0x40]
fcvt.s.bf16 fa0, ft0
# CHECK-ASM-AND-OBJ: fcvt.s.bf16 fa0, ft0, rup
# CHECK-ASM: encoding: [0x53,0x35,0x60,0x40]
fcvt.s.bf16 fa0, ft0, rup
# CHECK-ASM-AND-OBJ: fcvt.bf16.s ft2, fa2
# CHECK-ASM: encoding: [0x53,0x71,0x86,0x44]
fcvt.bf16.s ft2, fa2
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