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[RISCV] Custom promote f16/bf16 fp_to_(s/u)int to reduce isel patterns that emit two instructions. #107011

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Merged
merged 7 commits into from
Sep 3, 2024
Merged

[RISCV] Custom promote f16/bf16 fp_to_(s/u)int to reduce isel patterns that emit two instructions. #107011

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a99e613
[RISCV] Custom promote f16/bf16 fp_to_(s/u)int to reduce isel pattern…
topperc Sep 2, 2024
1fde3ed
fixup! Don't make STRICT_UINT_TO_FP/STRICT_SINT_TO_FP custom.
topperc Sep 2, 2024
5e50093
fixup! clang-format
topperc Sep 2, 2024
ed19367
fixup! fix typo in comment.
topperc Sep 2, 2024
03f9ad5
Merge remote-tracking branch 'origin/main' into pr/promote-fp-to-int
topperc Sep 3, 2024
c761dab
Merge remote-tracking branch 'origin/main' into pr/promote-fp-to-int
topperc Sep 3, 2024
0f81b25
Merge remote-tracking branch 'origin/main' into pr/promote-fp-to-int
topperc Sep 3, 2024
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32 changes: 31 additions & 1 deletion llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -460,6 +460,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FABS, MVT::bf16, Custom);
setOperationAction(ISD::FNEG, MVT::bf16, Custom);
setOperationAction(ISD::FCOPYSIGN, MVT::bf16, Custom);
setOperationAction({ISD::FP_TO_SINT, ISD::FP_TO_UINT}, XLenVT, Custom);
setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP}, XLenVT, Custom);
}

Expand All @@ -479,6 +480,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FABS, MVT::f16, Custom);
setOperationAction(ISD::FNEG, MVT::f16, Custom);
setOperationAction(ISD::FCOPYSIGN, MVT::f16, Custom);
setOperationAction({ISD::FP_TO_SINT, ISD::FP_TO_UINT}, XLenVT, Custom);
setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP}, XLenVT, Custom);
}

Expand Down Expand Up @@ -592,8 +594,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction({ISD::FP_TO_UINT_SAT, ISD::FP_TO_SINT_SAT}, XLenVT,
Custom);

// f16/bf16 require custom handling.
setOperationAction({ISD::STRICT_FP_TO_UINT, ISD::STRICT_FP_TO_SINT}, XLenVT,
Legal);
Custom);
setOperationAction({ISD::STRICT_UINT_TO_FP, ISD::STRICT_SINT_TO_FP}, XLenVT,
Custom);

Expand Down Expand Up @@ -3096,6 +3099,31 @@ static SDValue lowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG,
return Res;
}

static SDValue lowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
bool IsStrict = Op->isStrictFPOpcode();
SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);

// f16 conversions are promoted to f32 when Zfh/Zhinx is not enabled.
// bf16 conversions are always promoted to f32.
if ((SrcVal.getValueType() == MVT::f16 && !Subtarget.hasStdExtZfhOrZhinx()) ||
SrcVal.getValueType() == MVT::bf16) {
SDLoc DL(Op);
if (IsStrict) {
SDValue Ext =
DAG.getNode(ISD::STRICT_FP_EXTEND, DL, {MVT::f32, MVT::Other},
{Op.getOperand(0), SrcVal});
return DAG.getNode(Op.getOpcode(), DL, {Op.getValueType(), MVT::Other},
{Ext.getValue(1), Ext.getValue(0)});
}
return DAG.getNode(Op.getOpcode(), DL, Op.getValueType(),
DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, SrcVal));
}

// Other operations are legal.
return Op;
}

static RISCVFPRndMode::RoundingMode matchRoundingOp(unsigned Opc) {
switch (Opc) {
case ISD::FROUNDEVEN:
Expand Down Expand Up @@ -6661,6 +6689,8 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
// the source. We custom-lower any conversions that do two hops into
// sequences.
MVT VT = Op.getSimpleValueType();
if (VT.isScalarInteger())
return lowerFP_TO_INT(Op, DAG, Subtarget);
bool IsStrict = Op->isStrictFPOpcode();
SDValue Src = Op.getOperand(0 + IsStrict);
MVT SrcVT = Src.getSimpleValueType();
Expand Down
14 changes: 0 additions & 14 deletions llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
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Expand Up @@ -58,20 +58,6 @@ def : Pat<(riscv_fmv_x_anyexth (bf16 FPR16:$src)), (FMV_X_H FPR16:$src)>;
def : Pat<(riscv_fmv_x_signexth (bf16 FPR16:$src)), (FMV_X_H FPR16:$src)>;
} // Predicates = [HasStdExtZfbfmin]

let Predicates = [HasStdExtZfbfmin] in {
// bf16->[u]int. Round-to-zero must be used for the f32->int step, the
// rounding mode has no effect for bf16->f32.
def : Pat<(i32 (any_fp_to_sint (bf16 FPR16:$rs1))), (FCVT_W_S (FCVT_S_BF16 $rs1, FRM_RNE), FRM_RTZ)>;
def : Pat<(i32 (any_fp_to_uint (bf16 FPR16:$rs1))), (FCVT_WU_S (FCVT_S_BF16 $rs1, FRM_RNE), FRM_RTZ)>;
}

let Predicates = [HasStdExtZfbfmin, IsRV64] in {
// bf16->[u]int64. Round-to-zero must be used for the f32->int step, the
// rounding mode has no effect for bf16->f32.
def : Pat<(i64 (any_fp_to_sint (bf16 FPR16:$rs1))), (FCVT_L_S (FCVT_S_BF16 $rs1, FRM_RNE), FRM_RTZ)>;
def : Pat<(i64 (any_fp_to_uint (bf16 FPR16:$rs1))), (FCVT_LU_S (FCVT_S_BF16 $rs1, FRM_RNE), FRM_RTZ)>;
}

let Predicates = [HasStdExtZfbfmin, HasStdExtD] in {
// bf16 -> f64
def : Pat<(fpextend (bf16 FPR16:$rs1)),
Expand Down
24 changes: 0 additions & 24 deletions llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
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Original file line number Diff line number Diff line change
Expand Up @@ -599,27 +599,3 @@ def : Pat<(fcopysign FPR16INX:$rs1, FPR64INX:$rs2),
(FSGNJ_H_INX $rs1, (FCVT_H_D_INX $rs2, 0b111))>;
def : Pat<(fcopysign FPR64INX:$rs1, FPR16INX:$rs2), (FSGNJ_D_INX $rs1, (FCVT_D_H_INX $rs2, FRM_RNE))>;
} // Predicates = [HasStdExtZhinxmin, HasStdExtZdinx, IsRV64]

let Predicates = [HasStdExtZfhmin, NoStdExtZfh] in {
// half->[u]int. Round-to-zero must be used.
def : Pat<(i32 (any_fp_to_sint (f16 FPR16:$rs1))), (FCVT_W_S (FCVT_S_H $rs1, FRM_RNE), FRM_RTZ)>;
def : Pat<(i32 (any_fp_to_uint (f16 FPR16:$rs1))), (FCVT_WU_S (FCVT_S_H $rs1, FRM_RNE), FRM_RTZ)>;
} // Predicates = [HasStdExtZfhmin, NoStdExtZfh]

let Predicates = [HasStdExtZhinxmin, NoStdExtZhinx] in {
// half->[u]int. Round-to-zero must be used.
def : Pat<(i32 (any_fp_to_sint FPR16INX:$rs1)), (FCVT_W_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_RTZ)>;
def : Pat<(i32 (any_fp_to_uint FPR16INX:$rs1)), (FCVT_WU_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_RTZ)>;
} // Predicates = [HasStdExtZhinxmin, NoStdExtZhinx]

let Predicates = [HasStdExtZfhmin, NoStdExtZfh, IsRV64] in {
// half->[u]int64. Round-to-zero must be used.
def : Pat<(i64 (any_fp_to_sint (f16 FPR16:$rs1))), (FCVT_L_S (FCVT_S_H $rs1, FRM_RNE), FRM_RTZ)>;
def : Pat<(i64 (any_fp_to_uint (f16 FPR16:$rs1))), (FCVT_LU_S (FCVT_S_H $rs1, FRM_RNE), FRM_RTZ)>;
} // Predicates = [HasStdExtZfhmin, NoStdExtZfh, IsRV64]

let Predicates = [HasStdExtZhinxmin, NoStdExtZhinx, IsRV64] in {
// half->[u]int64. Round-to-zero must be used.
def : Pat<(i64 (any_fp_to_sint FPR16INX:$rs1)), (FCVT_L_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_RTZ)>;
def : Pat<(i64 (any_fp_to_uint FPR16INX:$rs1)), (FCVT_LU_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_RTZ)>;
} // Predicates = [HasStdExtZhinxmin, NoStdExtZhinx, IsRV64]
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/bfloat-convert.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -121,7 +121,7 @@ define i16 @fcvt_ui_bf16(bfloat %a) nounwind {
; CHECK32ZFBFMIN-LABEL: fcvt_ui_bf16:
; CHECK32ZFBFMIN: # %bb.0:
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
; CHECK32ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
; CHECK32ZFBFMIN-NEXT: ret
;
; RV32ID-LABEL: fcvt_ui_bf16:
Expand All @@ -135,7 +135,7 @@ define i16 @fcvt_ui_bf16(bfloat %a) nounwind {
; CHECK64ZFBFMIN-LABEL: fcvt_ui_bf16:
; CHECK64ZFBFMIN: # %bb.0:
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK64ZFBFMIN-NEXT: fcvt.lu.s a0, fa5, rtz
; CHECK64ZFBFMIN-NEXT: fcvt.l.s a0, fa5, rtz
; CHECK64ZFBFMIN-NEXT: ret
;
; RV64ID-LABEL: fcvt_ui_bf16:
Expand Down Expand Up @@ -1568,7 +1568,7 @@ define zeroext i8 @fcvt_wu_s_i8(bfloat %a) nounwind {
; CHECK32ZFBFMIN-LABEL: fcvt_wu_s_i8:
; CHECK32ZFBFMIN: # %bb.0:
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
; CHECK32ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
; CHECK32ZFBFMIN-NEXT: ret
;
; RV32ID-LABEL: fcvt_wu_s_i8:
Expand Down
28 changes: 14 additions & 14 deletions llvm/test/CodeGen/RISCV/half-convert-strict.ll
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Expand Up @@ -136,78 +136,78 @@ declare i16 @llvm.experimental.constrained.fptosi.i16.f16(half, metadata)
define i16 @fcvt_ui_h(half %a) nounwind strictfp {
; RV32IZFH-LABEL: fcvt_ui_h:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_ui_h:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
; RV64IZFH-NEXT: ret
;
; RV32IZHINX-LABEL: fcvt_ui_h:
; RV32IZHINX: # %bb.0:
; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: fcvt_ui_h:
; RV64IZHINX: # %bb.0:
; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
; RV64IZHINX-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_ui_h:
; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
; RV32IDZFH-NEXT: ret
;
; RV64IDZFH-LABEL: fcvt_ui_h:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.lu.h a0, fa0, rtz
; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rtz
; RV64IDZFH-NEXT: ret
;
; RV32IZDINXZHINX-LABEL: fcvt_ui_h:
; RV32IZDINXZHINX: # %bb.0:
; RV32IZDINXZHINX-NEXT: fcvt.wu.h a0, a0, rtz
; RV32IZDINXZHINX-NEXT: fcvt.w.h a0, a0, rtz
; RV32IZDINXZHINX-NEXT: ret
;
; RV64IZDINXZHINX-LABEL: fcvt_ui_h:
; RV64IZDINXZHINX: # %bb.0:
; RV64IZDINXZHINX-NEXT: fcvt.lu.h a0, a0, rtz
; RV64IZDINXZHINX-NEXT: fcvt.l.h a0, a0, rtz
; RV64IZDINXZHINX-NEXT: ret
;
; CHECK32-IZFHMIN-LABEL: fcvt_ui_h:
; CHECK32-IZFHMIN: # %bb.0:
; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
; CHECK32-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
; CHECK32-IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
; CHECK32-IZFHMIN-NEXT: ret
;
; CHECK64-IZFHMIN-LABEL: fcvt_ui_h:
; CHECK64-IZFHMIN: # %bb.0:
; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
; CHECK64-IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
; CHECK64-IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
; CHECK64-IZFHMIN-NEXT: ret
;
; CHECK32-IZHINXMIN-LABEL: fcvt_ui_h:
; CHECK32-IZHINXMIN: # %bb.0:
; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK32-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
; CHECK32-IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; CHECK32-IZHINXMIN-NEXT: ret
;
; CHECK64-IZHINXMIN-LABEL: fcvt_ui_h:
; CHECK64-IZHINXMIN: # %bb.0:
; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK64-IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
; CHECK64-IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
; CHECK64-IZHINXMIN-NEXT: ret
;
; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_ui_h:
; CHECK32-IZDINXZHINXMIN: # %bb.0:
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; CHECK32-IZDINXZHINXMIN-NEXT: ret
;
; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_ui_h:
; CHECK64-IZDINXZHINXMIN: # %bb.0:
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
; CHECK64-IZDINXZHINXMIN-NEXT: ret
%1 = call i16 @llvm.experimental.constrained.fptoui.i16.f16(half %a, metadata !"fpexcept.strict")
ret i16 %1
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/RISCV/half-convert.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -672,37 +672,37 @@ define i16 @fcvt_ui_h(half %a) nounwind {
; CHECK32-IZFHMIN-LABEL: fcvt_ui_h:
; CHECK32-IZFHMIN: # %bb.0:
; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
; CHECK32-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
; CHECK32-IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
; CHECK32-IZFHMIN-NEXT: ret
;
; CHECK64-IZFHMIN-LABEL: fcvt_ui_h:
; CHECK64-IZFHMIN: # %bb.0:
; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
; CHECK64-IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
; CHECK64-IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
; CHECK64-IZFHMIN-NEXT: ret
;
; CHECK32-IZHINXMIN-LABEL: fcvt_ui_h:
; CHECK32-IZHINXMIN: # %bb.0:
; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK32-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
; CHECK32-IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; CHECK32-IZHINXMIN-NEXT: ret
;
; CHECK64-IZHINXMIN-LABEL: fcvt_ui_h:
; CHECK64-IZHINXMIN: # %bb.0:
; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK64-IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
; CHECK64-IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
; CHECK64-IZHINXMIN-NEXT: ret
;
; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_ui_h:
; CHECK32-IZDINXZHINXMIN: # %bb.0:
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; CHECK32-IZDINXZHINXMIN-NEXT: ret
;
; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_ui_h:
; CHECK64-IZDINXZHINXMIN: # %bb.0:
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
; CHECK64-IZDINXZHINXMIN-NEXT: ret
%1 = fptoui half %a to i16
ret i16 %1
Expand Down Expand Up @@ -6793,7 +6793,7 @@ define zeroext i16 @fcvt_wu_s_i16(half %a) nounwind {
; CHECK32-IZFHMIN-LABEL: fcvt_wu_s_i16:
; CHECK32-IZFHMIN: # %bb.0:
; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
; CHECK32-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
; CHECK32-IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
; CHECK32-IZFHMIN-NEXT: ret
;
; CHECK64-IZFHMIN-LABEL: fcvt_wu_s_i16:
Expand All @@ -6805,7 +6805,7 @@ define zeroext i16 @fcvt_wu_s_i16(half %a) nounwind {
; CHECK32-IZHINXMIN-LABEL: fcvt_wu_s_i16:
; CHECK32-IZHINXMIN: # %bb.0:
; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK32-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
; CHECK32-IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; CHECK32-IZHINXMIN-NEXT: ret
;
; CHECK64-IZHINXMIN-LABEL: fcvt_wu_s_i16:
Expand All @@ -6817,7 +6817,7 @@ define zeroext i16 @fcvt_wu_s_i16(half %a) nounwind {
; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_wu_s_i16:
; CHECK32-IZDINXZHINXMIN: # %bb.0:
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; CHECK32-IZDINXZHINXMIN-NEXT: ret
;
; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_wu_s_i16:
Expand Down Expand Up @@ -7744,7 +7744,7 @@ define zeroext i8 @fcvt_wu_s_i8(half %a) nounwind {
; CHECK32-IZFHMIN-LABEL: fcvt_wu_s_i8:
; CHECK32-IZFHMIN: # %bb.0:
; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
; CHECK32-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
; CHECK32-IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
; CHECK32-IZFHMIN-NEXT: ret
;
; CHECK64-IZFHMIN-LABEL: fcvt_wu_s_i8:
Expand All @@ -7756,7 +7756,7 @@ define zeroext i8 @fcvt_wu_s_i8(half %a) nounwind {
; CHECK32-IZHINXMIN-LABEL: fcvt_wu_s_i8:
; CHECK32-IZHINXMIN: # %bb.0:
; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK32-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
; CHECK32-IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; CHECK32-IZHINXMIN-NEXT: ret
;
; CHECK64-IZHINXMIN-LABEL: fcvt_wu_s_i8:
Expand All @@ -7768,7 +7768,7 @@ define zeroext i8 @fcvt_wu_s_i8(half %a) nounwind {
; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_wu_s_i8:
; CHECK32-IZDINXZHINXMIN: # %bb.0:
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; CHECK32-IZDINXZHINXMIN-NEXT: ret
;
; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_wu_s_i8:
Expand Down
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