[RISCV] Custom promote f16/bf16 (s/u)int_to_fp. #107026
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This avoids having isel patterns that emit two instrutions. It also allows us to remove sext.w and slli+srli pairs by using fcvt.s.w(u) on RV64.
topperc
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@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesThis avoids having isel patterns that emit two instrutions. It also allows us to remove sext.w and slli+srli pairs by using fcvt.s.w(u) on RV64. Patch is 47.12 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/107026.diff 8 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 250d1c60b9f59e..eb7af7e951a3bf 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -460,6 +460,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FABS, MVT::bf16, Custom);
setOperationAction(ISD::FNEG, MVT::bf16, Custom);
setOperationAction(ISD::FCOPYSIGN, MVT::bf16, Expand);
+ setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP}, XLenVT, Custom);
}
if (Subtarget.hasStdExtZfhminOrZhinxmin()) {
@@ -478,6 +479,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FABS, MVT::f16, Custom);
setOperationAction(ISD::FNEG, MVT::f16, Custom);
setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
+ setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP}, XLenVT, Custom);
}
setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Legal);
@@ -590,9 +592,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction({ISD::FP_TO_UINT_SAT, ISD::FP_TO_SINT_SAT}, XLenVT,
Custom);
- setOperationAction({ISD::STRICT_FP_TO_UINT, ISD::STRICT_FP_TO_SINT,
- ISD::STRICT_UINT_TO_FP, ISD::STRICT_SINT_TO_FP},
+ setOperationAction({ISD::STRICT_FP_TO_UINT, ISD::STRICT_FP_TO_SINT},
XLenVT, Legal);
+ setOperationAction({ISD::STRICT_UINT_TO_FP, ISD::STRICT_SINT_TO_FP},
+ XLenVT, Custom);
setOperationAction(ISD::GET_ROUNDING, XLenVT, Custom);
setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
@@ -2953,6 +2956,31 @@ InstructionCost RISCVTargetLowering::getVSlideVICost(MVT VT) const {
return getLMULCost(VT);
}
+static SDValue lowerINT_TO_FP(SDValue Op, SelectionDAG &DAG,
+ const RISCVSubtarget &Subtarget) {
+ // f16 conversions are promoted to f32 when Zfh/Zhinx are not supported.
+ // bf16 conversions are always promoted to f32.
+ if ((Op.getValueType() == MVT::f16 && !Subtarget.hasStdExtZfhOrZhinx()) ||
+ Op.getValueType() == MVT::bf16) {
+ bool IsStrict = Op->isStrictFPOpcode();
+
+ SDLoc DL(Op);
+ if (IsStrict) {
+ SDValue Val = DAG.getNode(Op.getOpcode(), DL, {MVT::f32, MVT::Other},
+ {Op.getOperand(0), Op.getOperand(1)});
+ return DAG.getNode(
+ ISD::STRICT_FP_ROUND, DL, {Op.getValueType(), MVT::Other},
+ {Val.getValue(1), Val.getValue(0), DAG.getIntPtrConstant(0, DL, /*isTarget=*/true)});
+ }
+ return DAG.getNode(ISD::FP_ROUND, DL, Op.getValueType(),
+ DAG.getNode(Op.getOpcode(), DL, MVT::f32, Op.getOperand(0)),
+ DAG.getIntPtrConstant(0, DL, /*isTarget=*/true));
+ }
+
+ // Other operations are legal.
+ return Op;
+}
+
static SDValue lowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
// RISC-V FP-to-int conversions saturate to the destination register size, but
@@ -6568,13 +6596,15 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
// the source. We custom-lower any conversions that do two hops into
// sequences.
MVT VT = Op.getSimpleValueType();
+ bool IsStrict = Op->isStrictFPOpcode();
+ SDValue Src = Op.getOperand(0 + IsStrict);
+ MVT SrcVT = Src.getSimpleValueType();
+ if (SrcVT.isScalarInteger())
+ return lowerINT_TO_FP(Op, DAG, Subtarget);
if (!VT.isVector())
return Op;
SDLoc DL(Op);
- bool IsStrict = Op->isStrictFPOpcode();
- SDValue Src = Op.getOperand(0 + IsStrict);
MVT EltVT = VT.getVectorElementType();
- MVT SrcVT = Src.getSimpleValueType();
MVT SrcEltVT = SrcVT.getVectorElementType();
unsigned EltSize = EltVT.getSizeInBits();
unsigned SrcEltSize = SrcEltVT.getSizeInBits();
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
index bf6272317fda4d..753c53f1b466e3 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
@@ -63,10 +63,6 @@ let Predicates = [HasStdExtZfbfmin] in {
// rounding mode has no effect for bf16->f32.
def : Pat<(i32 (any_fp_to_sint (bf16 FPR16:$rs1))), (FCVT_W_S (FCVT_S_BF16 $rs1, FRM_RNE), FRM_RTZ)>;
def : Pat<(i32 (any_fp_to_uint (bf16 FPR16:$rs1))), (FCVT_WU_S (FCVT_S_BF16 $rs1, FRM_RNE), FRM_RTZ)>;
-
-// [u]int->bf16. Match GCC and default to using dynamic rounding mode.
-def : Pat<(bf16 (any_sint_to_fp (i32 GPR:$rs1))), (FCVT_BF16_S (FCVT_S_W $rs1, FRM_DYN), FRM_DYN)>;
-def : Pat<(bf16 (any_uint_to_fp (i32 GPR:$rs1))), (FCVT_BF16_S (FCVT_S_WU $rs1, FRM_DYN), FRM_DYN)>;
}
let Predicates = [HasStdExtZfbfmin, IsRV64] in {
@@ -74,10 +70,6 @@ let Predicates = [HasStdExtZfbfmin, IsRV64] in {
// rounding mode has no effect for bf16->f32.
def : Pat<(i64 (any_fp_to_sint (bf16 FPR16:$rs1))), (FCVT_L_S (FCVT_S_BF16 $rs1, FRM_RNE), FRM_RTZ)>;
def : Pat<(i64 (any_fp_to_uint (bf16 FPR16:$rs1))), (FCVT_LU_S (FCVT_S_BF16 $rs1, FRM_RNE), FRM_RTZ)>;
-
-// [u]int->bf16. Match GCC and default to using dynamic rounding mode.
-def : Pat<(bf16 (any_sint_to_fp (i64 GPR:$rs1))), (FCVT_BF16_S (FCVT_S_L $rs1, FRM_DYN), FRM_DYN)>;
-def : Pat<(bf16 (any_uint_to_fp (i64 GPR:$rs1))), (FCVT_BF16_S (FCVT_S_LU $rs1, FRM_DYN), FRM_DYN)>;
}
let Predicates = [HasStdExtZfbfmin, HasStdExtD] in {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
index d60cf33567d6d0..2f047a6dccdf46 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
@@ -604,38 +604,22 @@ let Predicates = [HasStdExtZfhmin, NoStdExtZfh] in {
// half->[u]int. Round-to-zero must be used.
def : Pat<(i32 (any_fp_to_sint (f16 FPR16:$rs1))), (FCVT_W_S (FCVT_S_H $rs1, FRM_RNE), FRM_RTZ)>;
def : Pat<(i32 (any_fp_to_uint (f16 FPR16:$rs1))), (FCVT_WU_S (FCVT_S_H $rs1, FRM_RNE), FRM_RTZ)>;
-
-// [u]int->half. Match GCC and default to using dynamic rounding mode.
-def : Pat<(f16 (any_sint_to_fp (i32 GPR:$rs1))), (FCVT_H_S (FCVT_S_W $rs1, FRM_DYN), FRM_DYN)>;
-def : Pat<(f16 (any_uint_to_fp (i32 GPR:$rs1))), (FCVT_H_S (FCVT_S_WU $rs1, FRM_DYN), FRM_DYN)>;
} // Predicates = [HasStdExtZfhmin, NoStdExtZfh]
let Predicates = [HasStdExtZhinxmin, NoStdExtZhinx] in {
// half->[u]int. Round-to-zero must be used.
def : Pat<(i32 (any_fp_to_sint FPR16INX:$rs1)), (FCVT_W_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_RTZ)>;
def : Pat<(i32 (any_fp_to_uint FPR16INX:$rs1)), (FCVT_WU_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_RTZ)>;
-
-// [u]int->half. Match GCC and default to using dynamic rounding mode.
-def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_H_S_INX (FCVT_S_W_INX $rs1, FRM_DYN), FRM_DYN)>;
-def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_H_S_INX (FCVT_S_WU_INX $rs1, FRM_DYN), FRM_DYN)>;
} // Predicates = [HasStdExtZhinxmin, NoStdExtZhinx]
let Predicates = [HasStdExtZfhmin, NoStdExtZfh, IsRV64] in {
// half->[u]int64. Round-to-zero must be used.
def : Pat<(i64 (any_fp_to_sint (f16 FPR16:$rs1))), (FCVT_L_S (FCVT_S_H $rs1, FRM_RNE), FRM_RTZ)>;
def : Pat<(i64 (any_fp_to_uint (f16 FPR16:$rs1))), (FCVT_LU_S (FCVT_S_H $rs1, FRM_RNE), FRM_RTZ)>;
-
-// [u]int->fp. Match GCC and default to using dynamic rounding mode.
-def : Pat<(f16 (any_sint_to_fp (i64 GPR:$rs1))), (FCVT_H_S (FCVT_S_L $rs1, FRM_DYN), FRM_DYN)>;
-def : Pat<(f16 (any_uint_to_fp (i64 GPR:$rs1))), (FCVT_H_S (FCVT_S_LU $rs1, FRM_DYN), FRM_DYN)>;
} // Predicates = [HasStdExtZfhmin, NoStdExtZfh, IsRV64]
let Predicates = [HasStdExtZhinxmin, NoStdExtZhinx, IsRV64] in {
// half->[u]int64. Round-to-zero must be used.
def : Pat<(i64 (any_fp_to_sint FPR16INX:$rs1)), (FCVT_L_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_RTZ)>;
def : Pat<(i64 (any_fp_to_uint FPR16INX:$rs1)), (FCVT_LU_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_RTZ)>;
-
-// [u]int->fp. Match GCC and default to using dynamic rounding mode.
-def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_H_S_INX (FCVT_S_L_INX $rs1, FRM_DYN), FRM_DYN)>;
-def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_H_S_INX (FCVT_S_LU_INX $rs1, FRM_DYN), FRM_DYN)>;
} // Predicates = [HasStdExtZhinxmin, NoStdExtZhinx, IsRV64]
diff --git a/llvm/test/CodeGen/RISCV/bfloat-convert.ll b/llvm/test/CodeGen/RISCV/bfloat-convert.ll
index 6d90def954bdb0..37ea80e6ae7726 100644
--- a/llvm/test/CodeGen/RISCV/bfloat-convert.ll
+++ b/llvm/test/CodeGen/RISCV/bfloat-convert.ll
@@ -749,7 +749,7 @@ define bfloat @fcvt_bf16_si(i16 %a) nounwind {
; CHECK64ZFBFMIN: # %bb.0:
; CHECK64ZFBFMIN-NEXT: slli a0, a0, 48
; CHECK64ZFBFMIN-NEXT: srai a0, a0, 48
-; CHECK64ZFBFMIN-NEXT: fcvt.s.l fa5, a0
+; CHECK64ZFBFMIN-NEXT: fcvt.s.w fa5, a0
; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
; CHECK64ZFBFMIN-NEXT: ret
;
@@ -795,7 +795,7 @@ define bfloat @fcvt_bf16_si_signext(i16 signext %a) nounwind {
;
; CHECK64ZFBFMIN-LABEL: fcvt_bf16_si_signext:
; CHECK64ZFBFMIN: # %bb.0:
-; CHECK64ZFBFMIN-NEXT: fcvt.s.l fa5, a0
+; CHECK64ZFBFMIN-NEXT: fcvt.s.w fa5, a0
; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
; CHECK64ZFBFMIN-NEXT: ret
;
@@ -845,7 +845,7 @@ define bfloat @fcvt_bf16_ui(i16 %a) nounwind {
; CHECK64ZFBFMIN: # %bb.0:
; CHECK64ZFBFMIN-NEXT: slli a0, a0, 48
; CHECK64ZFBFMIN-NEXT: srli a0, a0, 48
-; CHECK64ZFBFMIN-NEXT: fcvt.s.lu fa5, a0
+; CHECK64ZFBFMIN-NEXT: fcvt.s.wu fa5, a0
; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
; CHECK64ZFBFMIN-NEXT: ret
;
@@ -891,7 +891,7 @@ define bfloat @fcvt_bf16_ui_zeroext(i16 zeroext %a) nounwind {
;
; CHECK64ZFBFMIN-LABEL: fcvt_bf16_ui_zeroext:
; CHECK64ZFBFMIN: # %bb.0:
-; CHECK64ZFBFMIN-NEXT: fcvt.s.lu fa5, a0
+; CHECK64ZFBFMIN-NEXT: fcvt.s.wu fa5, a0
; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
; CHECK64ZFBFMIN-NEXT: ret
;
@@ -935,8 +935,7 @@ define bfloat @fcvt_bf16_w(i32 %a) nounwind {
;
; CHECK64ZFBFMIN-LABEL: fcvt_bf16_w:
; CHECK64ZFBFMIN: # %bb.0:
-; CHECK64ZFBFMIN-NEXT: sext.w a0, a0
-; CHECK64ZFBFMIN-NEXT: fcvt.s.l fa5, a0
+; CHECK64ZFBFMIN-NEXT: fcvt.s.w fa5, a0
; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
; CHECK64ZFBFMIN-NEXT: ret
;
@@ -983,7 +982,7 @@ define bfloat @fcvt_bf16_w_load(ptr %p) nounwind {
; CHECK64ZFBFMIN-LABEL: fcvt_bf16_w_load:
; CHECK64ZFBFMIN: # %bb.0:
; CHECK64ZFBFMIN-NEXT: lw a0, 0(a0)
-; CHECK64ZFBFMIN-NEXT: fcvt.s.l fa5, a0
+; CHECK64ZFBFMIN-NEXT: fcvt.s.w fa5, a0
; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
; CHECK64ZFBFMIN-NEXT: ret
;
@@ -1029,9 +1028,7 @@ define bfloat @fcvt_bf16_wu(i32 %a) nounwind {
;
; CHECK64ZFBFMIN-LABEL: fcvt_bf16_wu:
; CHECK64ZFBFMIN: # %bb.0:
-; CHECK64ZFBFMIN-NEXT: slli a0, a0, 32
-; CHECK64ZFBFMIN-NEXT: srli a0, a0, 32
-; CHECK64ZFBFMIN-NEXT: fcvt.s.lu fa5, a0
+; CHECK64ZFBFMIN-NEXT: fcvt.s.wu fa5, a0
; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
; CHECK64ZFBFMIN-NEXT: ret
;
@@ -1078,7 +1075,7 @@ define bfloat @fcvt_bf16_wu_load(ptr %p) nounwind {
; CHECK64ZFBFMIN-LABEL: fcvt_bf16_wu_load:
; CHECK64ZFBFMIN: # %bb.0:
; CHECK64ZFBFMIN-NEXT: lwu a0, 0(a0)
-; CHECK64ZFBFMIN-NEXT: fcvt.s.lu fa5, a0
+; CHECK64ZFBFMIN-NEXT: fcvt.s.wu fa5, a0
; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
; CHECK64ZFBFMIN-NEXT: ret
;
@@ -1376,7 +1373,7 @@ define signext i32 @fcvt_bf16_w_demanded_bits(i32 signext %0, ptr %1) nounwind {
; CHECK64ZFBFMIN-LABEL: fcvt_bf16_w_demanded_bits:
; CHECK64ZFBFMIN: # %bb.0:
; CHECK64ZFBFMIN-NEXT: addiw a0, a0, 1
-; CHECK64ZFBFMIN-NEXT: fcvt.s.l fa5, a0
+; CHECK64ZFBFMIN-NEXT: fcvt.s.w fa5, a0
; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa5, fa5
; CHECK64ZFBFMIN-NEXT: fsh fa5, 0(a1)
; CHECK64ZFBFMIN-NEXT: ret
@@ -1436,9 +1433,7 @@ define signext i32 @fcvt_bf16_wu_demanded_bits(i32 signext %0, ptr %1) nounwind
; CHECK64ZFBFMIN-LABEL: fcvt_bf16_wu_demanded_bits:
; CHECK64ZFBFMIN: # %bb.0:
; CHECK64ZFBFMIN-NEXT: addiw a0, a0, 1
-; CHECK64ZFBFMIN-NEXT: slli a2, a0, 32
-; CHECK64ZFBFMIN-NEXT: srli a2, a2, 32
-; CHECK64ZFBFMIN-NEXT: fcvt.s.lu fa5, a2
+; CHECK64ZFBFMIN-NEXT: fcvt.s.wu fa5, a0
; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa5, fa5
; CHECK64ZFBFMIN-NEXT: fsh fa5, 0(a1)
; CHECK64ZFBFMIN-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/half-convert-strict.ll b/llvm/test/CodeGen/RISCV/half-convert-strict.ll
index 8f88a4c570ea05..164d9a59e645cf 100644
--- a/llvm/test/CodeGen/RISCV/half-convert-strict.ll
+++ b/llvm/test/CodeGen/RISCV/half-convert-strict.ll
@@ -736,7 +736,7 @@ define half @fcvt_h_si(i16 %a) nounwind strictfp {
; CHECK64-IZFHMIN: # %bb.0:
; CHECK64-IZFHMIN-NEXT: slli a0, a0, 48
; CHECK64-IZFHMIN-NEXT: srai a0, a0, 48
-; CHECK64-IZFHMIN-NEXT: fcvt.s.l fa5, a0
+; CHECK64-IZFHMIN-NEXT: fcvt.s.w fa5, a0
; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECK64-IZFHMIN-NEXT: ret
;
@@ -752,7 +752,7 @@ define half @fcvt_h_si(i16 %a) nounwind strictfp {
; CHECK64-IZHINXMIN: # %bb.0:
; CHECK64-IZHINXMIN-NEXT: slli a0, a0, 48
; CHECK64-IZHINXMIN-NEXT: srai a0, a0, 48
-; CHECK64-IZHINXMIN-NEXT: fcvt.s.l a0, a0
+; CHECK64-IZHINXMIN-NEXT: fcvt.s.w a0, a0
; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECK64-IZHINXMIN-NEXT: ret
;
@@ -768,7 +768,7 @@ define half @fcvt_h_si(i16 %a) nounwind strictfp {
; CHECK64-IZDINXZHINXMIN: # %bb.0:
; CHECK64-IZDINXZHINXMIN-NEXT: slli a0, a0, 48
; CHECK64-IZDINXZHINXMIN-NEXT: srai a0, a0, 48
-; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.l a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.w a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: ret
%1 = call half @llvm.experimental.constrained.sitofp.f16.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -815,7 +815,7 @@ define half @fcvt_h_si_signext(i16 signext %a) nounwind strictfp {
;
; CHECK64-IZFHMIN-LABEL: fcvt_h_si_signext:
; CHECK64-IZFHMIN: # %bb.0:
-; CHECK64-IZFHMIN-NEXT: fcvt.s.l fa5, a0
+; CHECK64-IZFHMIN-NEXT: fcvt.s.w fa5, a0
; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECK64-IZFHMIN-NEXT: ret
;
@@ -827,7 +827,7 @@ define half @fcvt_h_si_signext(i16 signext %a) nounwind strictfp {
;
; CHECK64-IZHINXMIN-LABEL: fcvt_h_si_signext:
; CHECK64-IZHINXMIN: # %bb.0:
-; CHECK64-IZHINXMIN-NEXT: fcvt.s.l a0, a0
+; CHECK64-IZHINXMIN-NEXT: fcvt.s.w a0, a0
; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECK64-IZHINXMIN-NEXT: ret
;
@@ -839,7 +839,7 @@ define half @fcvt_h_si_signext(i16 signext %a) nounwind strictfp {
;
; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_si_signext:
; CHECK64-IZDINXZHINXMIN: # %bb.0:
-; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.l a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.w a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: ret
%1 = call half @llvm.experimental.constrained.sitofp.f16.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -915,7 +915,7 @@ define half @fcvt_h_ui(i16 %a) nounwind strictfp {
; CHECK64-IZFHMIN: # %bb.0:
; CHECK64-IZFHMIN-NEXT: slli a0, a0, 48
; CHECK64-IZFHMIN-NEXT: srli a0, a0, 48
-; CHECK64-IZFHMIN-NEXT: fcvt.s.lu fa5, a0
+; CHECK64-IZFHMIN-NEXT: fcvt.s.wu fa5, a0
; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECK64-IZFHMIN-NEXT: ret
;
@@ -931,7 +931,7 @@ define half @fcvt_h_ui(i16 %a) nounwind strictfp {
; CHECK64-IZHINXMIN: # %bb.0:
; CHECK64-IZHINXMIN-NEXT: slli a0, a0, 48
; CHECK64-IZHINXMIN-NEXT: srli a0, a0, 48
-; CHECK64-IZHINXMIN-NEXT: fcvt.s.lu a0, a0
+; CHECK64-IZHINXMIN-NEXT: fcvt.s.wu a0, a0
; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECK64-IZHINXMIN-NEXT: ret
;
@@ -947,7 +947,7 @@ define half @fcvt_h_ui(i16 %a) nounwind strictfp {
; CHECK64-IZDINXZHINXMIN: # %bb.0:
; CHECK64-IZDINXZHINXMIN-NEXT: slli a0, a0, 48
; CHECK64-IZDINXZHINXMIN-NEXT: srli a0, a0, 48
-; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.lu a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.wu a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: ret
%1 = call half @llvm.experimental.constrained.uitofp.f16.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -994,7 +994,7 @@ define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind strictfp {
;
; CHECK64-IZFHMIN-LABEL: fcvt_h_ui_zeroext:
; CHECK64-IZFHMIN: # %bb.0:
-; CHECK64-IZFHMIN-NEXT: fcvt.s.lu fa5, a0
+; CHECK64-IZFHMIN-NEXT: fcvt.s.wu fa5, a0
; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECK64-IZFHMIN-NEXT: ret
;
@@ -1006,7 +1006,7 @@ define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind strictfp {
;
; CHECK64-IZHINXMIN-LABEL: fcvt_h_ui_zeroext:
; CHECK64-IZHINXMIN: # %bb.0:
-; CHECK64-IZHINXMIN-NEXT: fcvt.s.lu a0, a0
+; CHECK64-IZHINXMIN-NEXT: fcvt.s.wu a0, a0
; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECK64-IZHINXMIN-NEXT: ret
;
@@ -1018,7 +1018,7 @@ define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind strictfp {
;
; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_ui_zeroext:
; CHECK64-IZDINXZHINXMIN: # %bb.0:
-; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.lu a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.wu a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: ret
%1 = call half @llvm.experimental.constrained.uitofp.f16.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -1064,8 +1064,7 @@ define half @fcvt_h_w(i32 %a) nounwind strictfp {
;
; CHECK64-IZFHMIN-LABEL: fcvt_h_w:
; CHECK64-IZFHMIN: # %bb.0:
-; CHECK64-IZFHMIN-NEXT: sext.w a0, a0
-; CHECK64-IZFHMIN-NEXT: fcvt.s.l fa5, a0
+; CHECK64-IZFHMIN-NEXT: fcvt.s.w fa5, a0
; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECK64-IZFHMIN-NEXT: ret
;
@@ -1077,8 +1076,7 @@ define half @fcvt_h_w(i32 %a) nounwind strictfp {
;
; CHECK64-IZHINXMIN-LABEL: fcvt_h_w:
; CHECK64-IZHINXMIN: # %bb.0:
-; CHECK64-IZHINXMIN-NEXT: sext.w a0, a0
-; CHECK64-IZHINXMIN-NEXT: fcvt.s.l a0, a0
+; CHECK64-IZHINXMIN-NEXT: fcvt.s.w a0, a0
; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECK64-IZHINXMIN-NEXT: ret
;
@@ -1090,8 +1088,7 @@ define half @fcvt_h_w(i32 %a) nounwind strictfp {
;
; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_w:
; CHECK64-IZDINXZHINXMIN: # %bb.0:
-; CHECK64-IZDINXZHINXMIN-NEXT: sext.w a0, a0
-; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.l a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.w a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: ret
%1 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -1146,7 +1143,7 @@ define half @fcvt_h_w_load(ptr %p) nounwind strictfp {
; CHECK64-IZFHMIN-LABEL: fcvt_h_w_load:
; CHECK64-IZFHMIN: # %bb.0:
; CHECK64-IZFHMIN-NEXT: lw a0, 0(a0)
-; CHECK64-IZFHMIN-NEXT: fcvt.s.l fa5, a0
+; CHECK64-IZFHMIN-NEXT: fcvt.s.w fa5, a0
; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECK64-IZFHMIN-NEXT: ret
;
@@ -1160,7 +1157,7 @@ define half @fcvt_h_w_load(ptr %p) nounwind strictfp {
; CHECK64-IZHINXMIN-LABEL: fcvt_h_w_load:
; CHECK64-IZHINXMIN: # %bb.0:
; CHECK64-IZHINXMIN-NEXT: lw a0, 0(a0)
-; CHECK64-IZHINXMIN-NEXT: fcvt.s.l a0, a0
+; CHECK64-IZHINXMIN-NEXT: fcvt.s.w a0, a0
; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECK64-IZHINXMIN-NEXT: ret
;
@@ -1174,7 +1171,7 @@ define half @fcvt_h_w_load(ptr %p) nounwind strictfp {
; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_w_load:
; CHECK64-IZDINXZHINXMIN: # %bb.0:
; CHECK64-IZDINXZHINXMIN-NEXT: lw a0, 0(a0)
-; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.l a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.w a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: ret
%a = load i32, ptr %p
@@ -1221,9 +1218,7 @@ define half @fcvt_h_wu(i32 %a) nounwind strictfp {
;
; CHECK64-IZFHMIN-LABEL: fcvt_h_wu:
; CHECK64-IZFHMIN: # %bb.0:
-; CHECK64-IZFHMIN-NEXT: slli a0, a0, 32
-; CHECK64-IZFHMIN-NEXT: srli a0, a0, 32
-; CHECK64-IZFHMIN-NEXT: fcvt.s.lu fa5, a0
+; CHECK64-IZFHMIN-NEXT: fcvt.s.wu fa5, a0
; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa0, fa5
...
[truncated]
|
|
✅ With the latest revision this PR passed the C/C++ code formatter. |
preames
approved these changes
Sep 3, 2024
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/59/builds/4265 Here is the relevant piece of the build log for the reference |
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This avoids having isel patterns that emit two instrutions. It also allows us to remove sext.w and slli+srli pairs by using fcvt.s.w(u) on RV64.