[RISCV] Correct the scheduler class for FCVT_S_BF16. #107028
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Use FCvtF16ToF32 instead of FCvtF32ToF16.
topperc
requested review from
asb,
jacquesguan,
dtcxzyw,
monkchiang and
wangpc-pp
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@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesUse FCvtF16ToF32 instead of FCvtF32ToF16. Full diff: https://github.com/llvm/llvm-project/pull/107028.diff 1 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
index bf6272317fda4d..52c4ee01bd44ac 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
@@ -31,7 +31,7 @@ let Predicates = [HasStdExtZfbfmin] in {
def FCVT_BF16_S : FPUnaryOp_r_frm<0b0100010, 0b01000, FPR16, FPR32, "fcvt.bf16.s">,
Sched<[WriteFCvtF32ToF16, ReadFCvtF32ToF16]>;
def FCVT_S_BF16 : FPUnaryOp_r_frm<0b0100000, 0b00110, FPR32, FPR16, "fcvt.s.bf16">,
- Sched<[WriteFCvtF32ToF16, ReadFCvtF32ToF16]>;
+ Sched<[WriteFCvtF16ToF32, ReadFCvtF16ToF32]>;
} // Predicates = [HasStdExtZfbfmin]
//===----------------------------------------------------------------------===//
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/30/builds/5291 Here is the relevant piece of the build log for the reference |
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Use FCvtF16ToF32 instead of FCvtF32ToF16.