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[RISCV] Update V0Defs after moving Src in peepholes #107359

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Merged
merged 2 commits into from
Sep 5, 2024
Merged

[RISCV] Update V0Defs after moving Src in peepholes #107359

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42fac4b
[RISCV] Update V0Defs after moving Src in peepholes
lukel97 Sep 5, 2024
1b0da29
Use V0Def of node being inserted before
lukel97 Sep 5, 2024
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15 changes: 8 additions & 7 deletions llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -61,7 +61,7 @@ class RISCVVectorPeephole : public MachineFunctionPass {
}

private:
bool tryToReduceVL(MachineInstr &MI) const;
bool tryToReduceVL(MachineInstr &MI);
bool convertToVLMAX(MachineInstr &MI) const;
bool convertToWholeRegister(MachineInstr &MI) const;
bool convertToUnmasked(MachineInstr &MI) const;
Expand All @@ -71,7 +71,7 @@ class RISCVVectorPeephole : public MachineFunctionPass {

bool isAllOnesMask(const MachineInstr *MaskDef) const;
std::optional<unsigned> getConstant(const MachineOperand &VL) const;
bool ensureDominates(const MachineOperand &Use, MachineInstr &Src) const;
bool ensureDominates(const MachineOperand &Use, MachineInstr &Src);

/// Maps uses of V0 to the corresponding def of V0.
DenseMap<const MachineInstr *, const MachineInstr *> V0Defs;
Expand Down Expand Up @@ -107,7 +107,7 @@ static unsigned getSEWLMULRatio(const MachineInstr &MI) {
// Attempt to reduce the VL of an instruction whose sole use is feeding a
// instruction with a narrower VL. This currently works backwards from the
// user instruction (which might have a smaller VL).
bool RISCVVectorPeephole::tryToReduceVL(MachineInstr &MI) const {
bool RISCVVectorPeephole::tryToReduceVL(MachineInstr &MI) {
// Note that the goal here is a bit multifaceted.
// 1) For store's reducing the VL of the value being stored may help to
// reduce VL toggles. This is somewhat of an artifact of the fact we
Expand Down Expand Up @@ -457,17 +457,18 @@ static bool dominates(MachineBasicBlock::const_iterator A,
/// does. Returns false if doesn't dominate and we can't move. \p MO must be in
/// the same basic block as \Src.
bool RISCVVectorPeephole::ensureDominates(const MachineOperand &MO,
MachineInstr &Src) const {
MachineInstr &Src) {
assert(MO.getParent()->getParent() == Src.getParent());
if (!MO.isReg() || MO.getReg() == RISCV::NoRegister)
return true;

MachineInstr *Def = MRI->getVRegDef(MO.getReg());
if (Def->getParent() == Src.getParent() && !dominates(Def, Src)) {
if (!isSafeToMove(Src, *Def->getNextNode()))
MachineInstr *AfterDef = Def->getNextNode();
if (!isSafeToMove(Src, *AfterDef))
return false;
// FIXME: Update V0Defs
Src.moveBefore(Def->getNextNode());
V0Defs[&Src] = V0Defs[AfterDef];
Src.moveBefore(AfterDef);
}

return true;
Expand Down
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