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[RISCV] Don't cost Fmv for Zfinx in isFPImmLegal. #107361

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Merged
merged 2 commits into from
Sep 5, 2024
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[RISCV] Don't cost Fmv for Zfinx in isFPImmLegal. #107361

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5af7a8e
[RISCV] Don't cost Fmv for Zfinx in isFPImmLegal.
topperc Sep 5, 2024
de508d2
fixup! fix typo
topperc Sep 5, 2024
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7 changes: 4 additions & 3 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2288,10 +2288,11 @@ bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
return true;

// Building an integer and then converting requires a fmv at the end of
// the integer sequence.
// the integer sequence. The fmv is not required for Zfinx.
const int FmvCost = Subtarget.hasStdExtZfinx() ? 0 : 1;
const int Cost =
1 + RISCVMatInt::getIntMatCost(Imm.bitcastToAPInt(), Subtarget.getXLen(),
Subtarget);
FmvCost + RISCVMatInt::getIntMatCost(Imm.bitcastToAPInt(),
Subtarget.getXLen(), Subtarget);
return Cost <= FPImmCost;
}

Expand Down
36 changes: 18 additions & 18 deletions llvm/test/CodeGen/RISCV/double-convert.ll
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Expand Up @@ -1668,16 +1668,16 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
;
; RV64IZFINXZDINX-LABEL: fcvt_w_s_sat_i16:
; RV64IZFINXZDINX: # %bb.0: # %start
; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI26_0)
; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI26_0)(a1)
; RV64IZFINXZDINX-NEXT: lui a2, %hi(.LCPI26_1)
; RV64IZFINXZDINX-NEXT: ld a2, %lo(.LCPI26_1)(a2)
; RV64IZFINXZDINX-NEXT: feq.d a3, a0, a0
; RV64IZFINXZDINX-NEXT: neg a3, a3
; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, a1
; RV64IZFINXZDINX-NEXT: feq.d a1, a0, a0
; RV64IZFINXZDINX-NEXT: neg a1, a1
; RV64IZFINXZDINX-NEXT: lui a2, %hi(.LCPI26_0)
; RV64IZFINXZDINX-NEXT: ld a2, %lo(.LCPI26_0)(a2)
; RV64IZFINXZDINX-NEXT: li a3, -505
; RV64IZFINXZDINX-NEXT: slli a3, a3, 53
; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, a3
; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a2
; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rtz
; RV64IZFINXZDINX-NEXT: and a0, a3, a0
; RV64IZFINXZDINX-NEXT: and a0, a1, a0
; RV64IZFINXZDINX-NEXT: ret
;
; RV32I-LABEL: fcvt_w_s_sat_i16:
Expand Down Expand Up @@ -2043,16 +2043,16 @@ define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind {
;
; RV64IZFINXZDINX-LABEL: fcvt_w_s_sat_i8:
; RV64IZFINXZDINX: # %bb.0: # %start
; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI30_0)
; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI30_0)(a1)
; RV64IZFINXZDINX-NEXT: lui a2, %hi(.LCPI30_1)
; RV64IZFINXZDINX-NEXT: ld a2, %lo(.LCPI30_1)(a2)
; RV64IZFINXZDINX-NEXT: feq.d a3, a0, a0
; RV64IZFINXZDINX-NEXT: neg a3, a3
; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, a1
; RV64IZFINXZDINX-NEXT: feq.d a1, a0, a0
; RV64IZFINXZDINX-NEXT: neg a1, a1
; RV64IZFINXZDINX-NEXT: li a2, -509
; RV64IZFINXZDINX-NEXT: slli a2, a2, 53
; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, a2
; RV64IZFINXZDINX-NEXT: lui a2, 65919
; RV64IZFINXZDINX-NEXT: slli a2, a2, 34
; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a2
; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rtz
; RV64IZFINXZDINX-NEXT: and a0, a3, a0
; RV64IZFINXZDINX-NEXT: and a0, a1, a0
; RV64IZFINXZDINX-NEXT: ret
;
; RV32I-LABEL: fcvt_w_s_sat_i8:
Expand Down Expand Up @@ -2234,9 +2234,9 @@ define zeroext i8 @fcvt_wu_s_sat_i8(double %a) nounwind {
;
; RV64IZFINXZDINX-LABEL: fcvt_wu_s_sat_i8:
; RV64IZFINXZDINX: # %bb.0: # %start
; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI32_0)
; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI32_0)(a1)
; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, zero
; RV64IZFINXZDINX-NEXT: lui a1, 131967
; RV64IZFINXZDINX-NEXT: slli a1, a1, 33
; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a1
; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rtz
; RV64IZFINXZDINX-NEXT: ret
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/double-imm.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -62,8 +62,8 @@ define double @double_imm_op(double %a) nounwind {
;
; CHECKRV64ZDINX-LABEL: double_imm_op:
; CHECKRV64ZDINX: # %bb.0:
; CHECKRV64ZDINX-NEXT: lui a1, %hi(.LCPI1_0)
; CHECKRV64ZDINX-NEXT: ld a1, %lo(.LCPI1_0)(a1)
; CHECKRV64ZDINX-NEXT: li a1, 1023
; CHECKRV64ZDINX-NEXT: slli a1, a1, 52
; CHECKRV64ZDINX-NEXT: fadd.d a0, a0, a1
; CHECKRV64ZDINX-NEXT: ret
%1 = fadd double %a, 1.0
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/RISCV/double-intrinsics.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -869,8 +869,8 @@ define double @floor_f64(double %a) nounwind {
;
; RV64IZFINXZDINX-LABEL: floor_f64:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI17_0)
; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI17_0)(a1)
; RV64IZFINXZDINX-NEXT: li a1, 1075
; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB17_2
Expand Down Expand Up @@ -934,8 +934,8 @@ define double @ceil_f64(double %a) nounwind {
;
; RV64IZFINXZDINX-LABEL: ceil_f64:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI18_0)
; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI18_0)(a1)
; RV64IZFINXZDINX-NEXT: li a1, 1075
; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB18_2
Expand Down Expand Up @@ -999,8 +999,8 @@ define double @trunc_f64(double %a) nounwind {
;
; RV64IZFINXZDINX-LABEL: trunc_f64:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI19_0)
; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI19_0)(a1)
; RV64IZFINXZDINX-NEXT: li a1, 1075
; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB19_2
Expand Down Expand Up @@ -1064,8 +1064,8 @@ define double @rint_f64(double %a) nounwind {
;
; RV64IZFINXZDINX-LABEL: rint_f64:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI20_0)
; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI20_0)(a1)
; RV64IZFINXZDINX-NEXT: li a1, 1075
; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB20_2
Expand Down Expand Up @@ -1170,8 +1170,8 @@ define double @round_f64(double %a) nounwind {
;
; RV64IZFINXZDINX-LABEL: round_f64:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI22_0)
; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI22_0)(a1)
; RV64IZFINXZDINX-NEXT: li a1, 1075
; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB22_2
Expand Down Expand Up @@ -1235,8 +1235,8 @@ define double @roundeven_f64(double %a) nounwind {
;
; RV64IZFINXZDINX-LABEL: roundeven_f64:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI23_0)
; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI23_0)(a1)
; RV64IZFINXZDINX-NEXT: li a1, 1075
; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB23_2
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/RISCV/double-round-conv.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1130,8 +1130,8 @@ define double @test_floor_double(double %x) {
;
; RV64IZFINXZDINX-LABEL: test_floor_double:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI40_0)
; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI40_0)(a1)
; RV64IZFINXZDINX-NEXT: li a1, 1075
; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB40_2
Expand Down Expand Up @@ -1177,8 +1177,8 @@ define double @test_ceil_double(double %x) {
;
; RV64IZFINXZDINX-LABEL: test_ceil_double:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI41_0)
; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI41_0)(a1)
; RV64IZFINXZDINX-NEXT: li a1, 1075
; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB41_2
Expand Down Expand Up @@ -1224,8 +1224,8 @@ define double @test_trunc_double(double %x) {
;
; RV64IZFINXZDINX-LABEL: test_trunc_double:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI42_0)
; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI42_0)(a1)
; RV64IZFINXZDINX-NEXT: li a1, 1075
; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB42_2
Expand Down Expand Up @@ -1271,8 +1271,8 @@ define double @test_round_double(double %x) {
;
; RV64IZFINXZDINX-LABEL: test_round_double:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI43_0)
; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI43_0)(a1)
; RV64IZFINXZDINX-NEXT: li a1, 1075
; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB43_2
Expand Down Expand Up @@ -1318,8 +1318,8 @@ define double @test_roundeven_double(double %x) {
;
; RV64IZFINXZDINX-LABEL: test_roundeven_double:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI44_0)
; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI44_0)(a1)
; RV64IZFINXZDINX-NEXT: li a1, 1075
; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
; RV64IZFINXZDINX-NEXT: beqz a1, .LBB44_2
Expand Down
32 changes: 16 additions & 16 deletions llvm/test/CodeGen/RISCV/float-convert.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -682,8 +682,8 @@ define i64 @fcvt_l_s_sat(float %a) nounwind {
; RV32IZFINX-NEXT: # %bb.1: # %start
; RV32IZFINX-NEXT: mv a2, a1
; RV32IZFINX-NEXT: .LBB12_2: # %start
; RV32IZFINX-NEXT: lui a1, %hi(.LCPI12_0)
; RV32IZFINX-NEXT: lw a1, %lo(.LCPI12_0)(a1)
; RV32IZFINX-NEXT: lui a1, 389120
; RV32IZFINX-NEXT: addi a1, a1, -1
; RV32IZFINX-NEXT: flt.s a3, a1, s0
; RV32IZFINX-NEXT: beqz a3, .LBB12_4
; RV32IZFINX-NEXT: # %bb.3:
Expand Down Expand Up @@ -910,9 +910,9 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind {
; RV32IZFINX-NEXT: neg s1, a0
; RV32IZFINX-NEXT: mv a0, s0
; RV32IZFINX-NEXT: call __fixunssfdi
; RV32IZFINX-NEXT: lui a2, %hi(.LCPI14_0)
; RV32IZFINX-NEXT: lw a2, %lo(.LCPI14_0)(a2)
; RV32IZFINX-NEXT: and a0, s1, a0
; RV32IZFINX-NEXT: lui a2, 391168
; RV32IZFINX-NEXT: addi a2, a2, -1
; RV32IZFINX-NEXT: flt.s a2, a2, s0
; RV32IZFINX-NEXT: neg a2, a2
; RV32IZFINX-NEXT: or a0, a2, a0
Expand Down Expand Up @@ -1445,11 +1445,11 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
; RV32IZFINX-LABEL: fcvt_w_s_sat_i16:
; RV32IZFINX: # %bb.0: # %start
; RV32IZFINX-NEXT: feq.s a1, a0, a0
; RV32IZFINX-NEXT: lui a2, %hi(.LCPI24_0)
; RV32IZFINX-NEXT: lw a2, %lo(.LCPI24_0)(a2)
; RV32IZFINX-NEXT: neg a1, a1
; RV32IZFINX-NEXT: lui a3, 815104
; RV32IZFINX-NEXT: fmax.s a0, a0, a3
; RV32IZFINX-NEXT: lui a2, 815104
; RV32IZFINX-NEXT: fmax.s a0, a0, a2
; RV32IZFINX-NEXT: lui a2, 290816
; RV32IZFINX-NEXT: addi a2, a2, -512
; RV32IZFINX-NEXT: fmin.s a0, a0, a2
; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rtz
; RV32IZFINX-NEXT: and a0, a1, a0
Expand All @@ -1458,11 +1458,11 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
; RV64IZFINX-LABEL: fcvt_w_s_sat_i16:
; RV64IZFINX: # %bb.0: # %start
; RV64IZFINX-NEXT: feq.s a1, a0, a0
; RV64IZFINX-NEXT: lui a2, %hi(.LCPI24_0)
; RV64IZFINX-NEXT: lw a2, %lo(.LCPI24_0)(a2)
; RV64IZFINX-NEXT: neg a1, a1
; RV64IZFINX-NEXT: lui a3, 815104
; RV64IZFINX-NEXT: fmax.s a0, a0, a3
; RV64IZFINX-NEXT: lui a2, 815104
; RV64IZFINX-NEXT: fmax.s a0, a0, a2
; RV64IZFINX-NEXT: lui a2, 290816
; RV64IZFINX-NEXT: addiw a2, a2, -512
; RV64IZFINX-NEXT: fmin.s a0, a0, a2
; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz
; RV64IZFINX-NEXT: and a0, a1, a0
Expand Down Expand Up @@ -1622,18 +1622,18 @@ define zeroext i16 @fcvt_wu_s_sat_i16(float %a) nounwind {
;
; RV32IZFINX-LABEL: fcvt_wu_s_sat_i16:
; RV32IZFINX: # %bb.0: # %start
; RV32IZFINX-NEXT: lui a1, %hi(.LCPI26_0)
; RV32IZFINX-NEXT: lw a1, %lo(.LCPI26_0)(a1)
; RV32IZFINX-NEXT: fmax.s a0, a0, zero
; RV32IZFINX-NEXT: lui a1, 292864
; RV32IZFINX-NEXT: addi a1, a1, -256
; RV32IZFINX-NEXT: fmin.s a0, a0, a1
; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rtz
; RV32IZFINX-NEXT: ret
;
; RV64IZFINX-LABEL: fcvt_wu_s_sat_i16:
; RV64IZFINX: # %bb.0: # %start
; RV64IZFINX-NEXT: lui a1, %hi(.LCPI26_0)
; RV64IZFINX-NEXT: lw a1, %lo(.LCPI26_0)(a1)
; RV64IZFINX-NEXT: fmax.s a0, a0, zero
; RV64IZFINX-NEXT: lui a1, 292864
; RV64IZFINX-NEXT: addiw a1, a1, -256
; RV64IZFINX-NEXT: fmin.s a0, a0, a1
; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz
; RV64IZFINX-NEXT: ret
Expand Down
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