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[RISCV] Restructure CC_RISCV_FastCC to reduce code duplication. NFC #107671

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Merged
merged 1 commit into from
Sep 12, 2024
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[RISCV] Restructure CC_RISCV_FastCC to reduce code duplication. NFC #107671

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64 changes: 20 additions & 44 deletions llvm/lib/Target/RISCV/RISCVCallingConv.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -524,13 +524,6 @@ bool llvm::CC_RISCV_FastCC(unsigned ValNo, MVT ValVT, MVT LocVT,
const RISCVTargetLowering &TLI = *Subtarget.getTargetLowering();
RISCVABI::ABI ABI = Subtarget.getTargetABI();

if (LocVT == MVT::i32 || LocVT == MVT::i64) {
if (MCRegister Reg = State.AllocateReg(getFastCCArgGPRs(ABI))) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
}

if ((LocVT == MVT::f16 && Subtarget.hasStdExtZfhmin()) ||
(LocVT == MVT::bf16 && Subtarget.hasStdExtZfbfmin())) {
static const MCPhysReg FPR16List[] = {
Expand Down Expand Up @@ -568,14 +561,16 @@ bool llvm::CC_RISCV_FastCC(unsigned ValNo, MVT ValVT, MVT LocVT,
}
}

MVT XLenVT = Subtarget.getXLenVT();

// Check if there is an available GPR before hitting the stack.
if ((LocVT == MVT::f16 && Subtarget.hasStdExtZhinxmin()) ||
(LocVT == MVT::f32 && Subtarget.hasStdExtZfinx()) ||
(LocVT == MVT::f64 && Subtarget.is64Bit() &&
Subtarget.hasStdExtZdinx())) {
if (MCRegister Reg = State.AllocateReg(getFastCCArgGPRs(ABI))) {
if (LocVT.getSizeInBits() != Subtarget.getXLen()) {
LocVT = Subtarget.getXLenVT();
LocVT = XLenVT;
State.addLoc(
CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
Expand All @@ -585,58 +580,39 @@ bool llvm::CC_RISCV_FastCC(unsigned ValNo, MVT ValVT, MVT LocVT,
}
}

if (LocVT == MVT::f16 || LocVT == MVT::bf16) {
int64_t Offset2 = State.AllocateStack(2, Align(2));
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
return false;
}

if (LocVT == MVT::i32 || LocVT == MVT::f32) {
int64_t Offset4 = State.AllocateStack(4, Align(4));
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
return false;
}

if (LocVT == MVT::i64 || LocVT == MVT::f64) {
int64_t Offset5 = State.AllocateStack(8, Align(8));
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
return false;
}
ArrayRef<MCPhysReg> ArgGPRs = getFastCCArgGPRs(ABI);

if (LocVT.isVector()) {
if (MCRegister Reg = allocateRVVReg(ValVT, ValNo, State, TLI)) {
// Fixed-length vectors are located in the corresponding scalable-vector
// container types.
if (ValVT.isFixedLengthVector())
if (LocVT.isFixedLengthVector())
LocVT = TLI.getContainerForFixedLengthVector(LocVT);
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}

// Try and pass the address via a "fast" GPR.
if (MCRegister GPRReg = State.AllocateReg(getFastCCArgGPRs(ABI))) {
// Pass scalable vectors indirectly. Pass fixed vectors indirectly if we
// have a free GPR.
if (LocVT.isScalableVector() ||
State.getFirstUnallocated(ArgGPRs) != ArgGPRs.size()) {
LocInfo = CCValAssign::Indirect;
LocVT = Subtarget.getXLenVT();
State.addLoc(CCValAssign::getReg(ValNo, ValVT, GPRReg, LocVT, LocInfo));
return false;
LocVT = XLenVT;
}
}

// Pass scalable vectors indirectly by storing the pointer on the stack.
if (ValVT.isScalableVector()) {
LocInfo = CCValAssign::Indirect;
LocVT = Subtarget.getXLenVT();
unsigned XLen = Subtarget.getXLen();
int64_t StackOffset = State.AllocateStack(XLen / 8, Align(XLen / 8));
State.addLoc(
CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo));
if (LocVT == XLenVT) {
if (MCRegister Reg = State.AllocateReg(getFastCCArgGPRs(ABI))) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
}

// Pass fixed-length vectors on the stack.
auto StackAlign = MaybeAlign(ValVT.getScalarSizeInBits() / 8).valueOrOne();
int64_t StackOffset = State.AllocateStack(ValVT.getStoreSize(), StackAlign);
State.addLoc(
CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo));
if (LocVT == XLenVT || LocVT == MVT::f16 || LocVT == MVT::bf16 ||
LocVT == MVT::f32 || LocVT == MVT::f64 || LocVT.isFixedLengthVector()) {
Align StackAlign = MaybeAlign(ValVT.getScalarSizeInBits() / 8).valueOrOne();
int64_t Offset = State.AllocateStack(LocVT.getStoreSize(), StackAlign);
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
return false;
}

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