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Merged
merged 4 commits into from
Sep 13, 2024
Merged

[X86] AMD Zen 5 Initial enablement #107964

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b68bcc1
[X86] AMD Zen 5 Initial enablement
ganeshgit Aug 29, 2024
12f2432
Update for formatting errors.
ganeshgit Sep 13, 2024
f00dbbf
Fix clang-format errors
ganeshgit Sep 13, 2024
cedee6b
Merge branch 'main' into znver5
ganeshgit Sep 13, 2024
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4 changes: 4 additions & 0 deletions clang/lib/Basic/Targets/X86.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -728,6 +728,9 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
case CK_ZNVER4:
defineCPUMacros(Builder, "znver4");
break;
case CK_ZNVER5:
defineCPUMacros(Builder, "znver5");
break;
case CK_Geode:
defineCPUMacros(Builder, "geode");
break;
Expand Down Expand Up @@ -1626,6 +1629,7 @@ std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
case CK_ZNVER2:
case CK_ZNVER3:
case CK_ZNVER4:
case CK_ZNVER5:
// Deprecated
case CK_x86_64:
case CK_x86_64_v2:
Expand Down
1 change: 1 addition & 0 deletions clang/test/CodeGen/target-builtin-noerror.c
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Expand Up @@ -207,4 +207,5 @@ void verifycpustrings(void) {
(void)__builtin_cpu_is("znver2");
(void)__builtin_cpu_is("znver3");
(void)__builtin_cpu_is("znver4");
(void)__builtin_cpu_is("znver5");
}
4 changes: 4 additions & 0 deletions clang/test/Driver/x86-march.c
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Expand Up @@ -242,6 +242,10 @@
// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=znver4 2>&1 \
// RUN: | FileCheck %s -check-prefix=znver4
// znver4: "-target-cpu" "znver4"
//
// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=znver5 2>&1 \
// RUN: | FileCheck %s -check-prefix=znver5
// znver5: "-target-cpu" "znver5"

// RUN: %clang -target x86_64 -c -### %s -march=x86-64 2>&1 | FileCheck %s --check-prefix=x86-64
// x86-64: "-target-cpu" "x86-64"
Expand Down
1 change: 1 addition & 0 deletions clang/test/Frontend/x86-target-cpu.c
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Expand Up @@ -38,5 +38,6 @@
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver2 -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver3 -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver4 -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver5 -verify %s
//
// expected-no-diagnostics
4 changes: 4 additions & 0 deletions clang/test/Misc/target-invalid-cpu-note/x86.c
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Expand Up @@ -99,6 +99,7 @@
// X86-SAME: {{^}}, znver2
// X86-SAME: {{^}}, znver3
// X86-SAME: {{^}}, znver4
// X86-SAME: {{^}}, znver5
// X86-SAME: {{^}}, x86-64
// X86-SAME: {{^}}, x86-64-v2
// X86-SAME: {{^}}, x86-64-v3
Expand Down Expand Up @@ -175,6 +176,7 @@
// X86_64-SAME: {{^}}, znver2
// X86_64-SAME: {{^}}, znver3
// X86_64-SAME: {{^}}, znver4
// X86_64-SAME: {{^}}, znver5
// X86_64-SAME: {{^}}, x86-64
// X86_64-SAME: {{^}}, x86-64-v2
// X86_64-SAME: {{^}}, x86-64-v3
Expand Down Expand Up @@ -278,6 +280,7 @@
// TUNE_X86-SAME: {{^}}, znver2
// TUNE_X86-SAME: {{^}}, znver3
// TUNE_X86-SAME: {{^}}, znver4
// TUNE_X86-SAME: {{^}}, znver5
// TUNE_X86-SAME: {{^}}, x86-64
// TUNE_X86-SAME: {{^}}, geode
// TUNE_X86-SAME: {{$}}
Expand Down Expand Up @@ -379,6 +382,7 @@
// TUNE_X86_64-SAME: {{^}}, znver2
// TUNE_X86_64-SAME: {{^}}, znver3
// TUNE_X86_64-SAME: {{^}}, znver4
// TUNE_X86_64-SAME: {{^}}, znver5
// TUNE_X86_64-SAME: {{^}}, x86-64
// TUNE_X86_64-SAME: {{^}}, geode
// TUNE_X86_64-SAME: {{$}}
142 changes: 142 additions & 0 deletions clang/test/Preprocessor/predefined-arch-macros.c
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Expand Up @@ -3923,6 +3923,148 @@
// CHECK_ZNVER4_M64: #define __znver4 1
// CHECK_ZNVER4_M64: #define __znver4__ 1

// RUN: %clang -march=znver5 -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ZNVER5_M32
// CHECK_ZNVER5_M32-NOT: #define __3dNOW_A__ 1
// CHECK_ZNVER5_M32-NOT: #define __3dNOW__ 1
// CHECK_ZNVER5_M32: #define __ADX__ 1
// CHECK_ZNVER5_M32: #define __AES__ 1
// CHECK_ZNVER5_M32: #define __AVX2__ 1
// CHECK_ZNVER5_M32: #define __AVX512BF16__ 1
// CHECK_ZNVER5_M32: #define __AVX512BITALG__ 1
// CHECK_ZNVER5_M32: #define __AVX512BW__ 1
// CHECK_ZNVER5_M32: #define __AVX512CD__ 1
// CHECK_ZNVER5_M32: #define __AVX512DQ__ 1
// CHECK_ZNVER5_M32: #define __AVX512F__ 1
// CHECK_ZNVER5_M32: #define __AVX512IFMA__ 1
// CHECK_ZNVER5_M32: #define __AVX512VBMI2__ 1
// CHECK_ZNVER5_M32: #define __AVX512VBMI__ 1
// CHECK_ZNVER5_M32: #define __AVX512VL__ 1
// CHECK_ZNVER5_M32: #define __AVX512VNNI__ 1
// CHECK_ZNVER5_M32: #define __AVX512VP2INTERSECT__ 1
// CHECK_ZNVER5_M32: #define __AVX512VPOPCNTDQ__ 1
// CHECK_ZNVER5_M32: #define __AVXVNNI__ 1
// CHECK_ZNVER5_M32: #define __AVX__ 1
// CHECK_ZNVER5_M32: #define __BMI2__ 1
// CHECK_ZNVER5_M32: #define __BMI__ 1
// CHECK_ZNVER5_M32: #define __CLFLUSHOPT__ 1
// CHECK_ZNVER5_M32: #define __CLWB__ 1
// CHECK_ZNVER5_M32: #define __CLZERO__ 1
// CHECK_ZNVER5_M32: #define __F16C__ 1
// CHECK_ZNVER5_M32-NOT: #define __FMA4__ 1
// CHECK_ZNVER5_M32: #define __FMA__ 1
// CHECK_ZNVER5_M32: #define __FSGSBASE__ 1
// CHECK_ZNVER5_M32: #define __GFNI__ 1
// CHECK_ZNVER5_M32: #define __LZCNT__ 1
// CHECK_ZNVER5_M32: #define __MMX__ 1
// CHECK_ZNVER5_M32: #define __MOVDIR64B__ 1
// CHECK_ZNVER5_M32: #define __MOVDIRI__ 1
// CHECK_ZNVER5_M32: #define __PCLMUL__ 1
// CHECK_ZNVER5_M32: #define __PKU__ 1
// CHECK_ZNVER5_M32: #define __POPCNT__ 1
// CHECK_ZNVER5_M32: #define __PREFETCHI__ 1
// CHECK_ZNVER5_M32: #define __PRFCHW__ 1
// CHECK_ZNVER5_M32: #define __RDPID__ 1
// CHECK_ZNVER5_M32: #define __RDPRU__ 1
// CHECK_ZNVER5_M32: #define __RDRND__ 1
// CHECK_ZNVER5_M32: #define __RDSEED__ 1
// CHECK_ZNVER5_M32: #define __SHA__ 1
// CHECK_ZNVER5_M32: #define __SSE2_MATH__ 1
// CHECK_ZNVER5_M32: #define __SSE2__ 1
// CHECK_ZNVER5_M32: #define __SSE3__ 1
// CHECK_ZNVER5_M32: #define __SSE4A__ 1
// CHECK_ZNVER5_M32: #define __SSE4_1__ 1
// CHECK_ZNVER5_M32: #define __SSE4_2__ 1
// CHECK_ZNVER5_M32: #define __SSE_MATH__ 1
// CHECK_ZNVER5_M32: #define __SSE__ 1
// CHECK_ZNVER5_M32: #define __SSSE3__ 1
// CHECK_ZNVER5_M32-NOT: #define __TBM__ 1
// CHECK_ZNVER5_M32: #define __WBNOINVD__ 1
// CHECK_ZNVER5_M32-NOT: #define __XOP__ 1
// CHECK_ZNVER5_M32: #define __XSAVEC__ 1
// CHECK_ZNVER5_M32: #define __XSAVEOPT__ 1
// CHECK_ZNVER5_M32: #define __XSAVES__ 1
// CHECK_ZNVER5_M32: #define __XSAVE__ 1
// CHECK_ZNVER5_M32: #define __i386 1
// CHECK_ZNVER5_M32: #define __i386__ 1
// CHECK_ZNVER5_M32: #define __tune_znver5__ 1
// CHECK_ZNVER5_M32: #define __znver5 1
// CHECK_ZNVER5_M32: #define __znver5__ 1

// RUN: %clang -march=znver5 -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ZNVER5_M64
// CHECK_ZNVER5_M64-NOT: #define __3dNOW_A__ 1
// CHECK_ZNVER5_M64-NOT: #define __3dNOW__ 1
// CHECK_ZNVER5_M64: #define __ADX__ 1
// CHECK_ZNVER5_M64: #define __AES__ 1
// CHECK_ZNVER5_M64: #define __AVX2__ 1
// CHECK_ZNVER5_M64: #define __AVX512BF16__ 1
// CHECK_ZNVER5_M64: #define __AVX512BITALG__ 1
// CHECK_ZNVER5_M64: #define __AVX512BW__ 1
// CHECK_ZNVER5_M64: #define __AVX512CD__ 1
// CHECK_ZNVER5_M64: #define __AVX512DQ__ 1
// CHECK_ZNVER5_M64: #define __AVX512F__ 1
// CHECK_ZNVER5_M64: #define __AVX512IFMA__ 1
// CHECK_ZNVER5_M64: #define __AVX512VBMI2__ 1
// CHECK_ZNVER5_M64: #define __AVX512VBMI__ 1
// CHECK_ZNVER5_M64: #define __AVX512VL__ 1
// CHECK_ZNVER5_M64: #define __AVX512VNNI__ 1
// CHECK_ZNVER5_M64: #define __AVX512VP2INTERSECT__ 1
// CHECK_ZNVER5_M64: #define __AVX512VPOPCNTDQ__ 1
// CHECK_ZNVER5_M64: #define __AVXVNNI__ 1
// CHECK_ZNVER5_M64: #define __AVX__ 1
// CHECK_ZNVER5_M64: #define __BMI2__ 1
// CHECK_ZNVER5_M64: #define __BMI__ 1
// CHECK_ZNVER5_M64: #define __CLFLUSHOPT__ 1
// CHECK_ZNVER5_M64: #define __CLWB__ 1
// CHECK_ZNVER5_M64: #define __CLZERO__ 1
// CHECK_ZNVER5_M64: #define __F16C__ 1
// CHECK_ZNVER5_M64-NOT: #define __FMA4__ 1
// CHECK_ZNVER5_M64: #define __FMA__ 1
// CHECK_ZNVER5_M64: #define __FSGSBASE__ 1
// CHECK_ZNVER5_M64: #define __GFNI__ 1
// CHECK_ZNVER5_M64: #define __LZCNT__ 1
// CHECK_ZNVER5_M64: #define __MMX__ 1
// CHECK_ZNVER5_M64: #define __MOVDIR64B__ 1
// CHECK_ZNVER5_M64: #define __MOVDIRI__ 1
// CHECK_ZNVER5_M64: #define __PCLMUL__ 1
// CHECK_ZNVER5_M64: #define __PKU__ 1
// CHECK_ZNVER5_M64: #define __POPCNT__ 1
// CHECK_ZNVER5_M64: #define __PREFETCHI__ 1
// CHECK_ZNVER5_M64: #define __PRFCHW__ 1
// CHECK_ZNVER5_M64: #define __RDPID__ 1
// CHECK_ZNVER5_M64: #define __RDPRU__ 1
// CHECK_ZNVER5_M64: #define __RDRND__ 1
// CHECK_ZNVER5_M64: #define __RDSEED__ 1
// CHECK_ZNVER5_M64: #define __SHA__ 1
// CHECK_ZNVER5_M64: #define __SSE2_MATH__ 1
// CHECK_ZNVER5_M64: #define __SSE2__ 1
// CHECK_ZNVER5_M64: #define __SSE3__ 1
// CHECK_ZNVER5_M64: #define __SSE4A__ 1
// CHECK_ZNVER5_M64: #define __SSE4_1__ 1
// CHECK_ZNVER5_M64: #define __SSE4_2__ 1
// CHECK_ZNVER5_M64: #define __SSE_MATH__ 1
// CHECK_ZNVER5_M64: #define __SSE__ 1
// CHECK_ZNVER5_M64: #define __SSSE3__ 1
// CHECK_ZNVER5_M64-NOT: #define __TBM__ 1
// CHECK_ZNVER5_M64: #define __VAES__ 1
// CHECK_ZNVER5_M64: #define __VPCLMULQDQ__ 1
// CHECK_ZNVER5_M64: #define __WBNOINVD__ 1
// CHECK_ZNVER5_M64-NOT: #define __XOP__ 1
// CHECK_ZNVER5_M64: #define __XSAVEC__ 1
// CHECK_ZNVER5_M64: #define __XSAVEOPT__ 1
// CHECK_ZNVER5_M64: #define __XSAVES__ 1
// CHECK_ZNVER5_M64: #define __XSAVE__ 1
// CHECK_ZNVER5_M64: #define __amd64 1
// CHECK_ZNVER5_M64: #define __amd64__ 1
// CHECK_ZNVER5_M64: #define __tune_znver5__ 1
// CHECK_ZNVER5_M64: #define __x86_64 1
// CHECK_ZNVER5_M64: #define __x86_64__ 1
// CHECK_ZNVER5_M64: #define __znver5 1
// CHECK_ZNVER5_M64: #define __znver5__ 1

// End X86/GCC/Linux tests ------------------

// Begin PPC/GCC/Linux tests ----------------
Expand Down
20 changes: 20 additions & 0 deletions compiler-rt/lib/builtins/cpu_model/x86.c
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Expand Up @@ -63,6 +63,7 @@ enum ProcessorTypes {
INTEL_SIERRAFOREST,
INTEL_GRANDRIDGE,
INTEL_CLEARWATERFOREST,
AMDFAM1AH,
CPU_TYPE_MAX
};

Expand Down Expand Up @@ -101,6 +102,7 @@ enum ProcessorSubtypes {
INTEL_COREI7_ARROWLAKE,
INTEL_COREI7_ARROWLAKE_S,
INTEL_COREI7_PANTHERLAKE,
AMDFAM1AH_ZNVER5,
CPU_SUBTYPE_MAX
};

Expand Down Expand Up @@ -748,6 +750,24 @@ static const char *getAMDProcessorTypeAndSubtype(unsigned Family,
break; // "znver4"
}
break; // family 19h
case 26:
CPU = "znver5";
*Type = AMDFAM1AH;
if (Model <= 0x77) {
// Models 00h-0Fh (Breithorn).
// Models 10h-1Fh (Breithorn-Dense).
// Models 20h-2Fh (Strix 1).
// Models 30h-37h (Strix 2).
// Models 38h-3Fh (Strix 3).
// Models 40h-4Fh (Granite Ridge).
// Models 50h-5Fh (Weisshorn).
// Models 60h-6Fh (Krackan1).
// Models 70h-77h (Sarlak).
CPU = "znver5";
*Subtype = AMDFAM1AH_ZNVER5;
break; // "znver5"
}
break;
default:
break; // Unknown AMD CPU.
}
Expand Down
3 changes: 3 additions & 0 deletions llvm/include/llvm/TargetParser/X86TargetParser.def
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Expand Up @@ -49,11 +49,13 @@ X86_CPU_TYPE(ZHAOXIN_FAM7H, "zhaoxin_fam7h")
X86_CPU_TYPE(INTEL_SIERRAFOREST, "sierraforest")
X86_CPU_TYPE(INTEL_GRANDRIDGE, "grandridge")
X86_CPU_TYPE(INTEL_CLEARWATERFOREST, "clearwaterforest")
X86_CPU_TYPE(AMDFAM1AH, "amdfam1ah")

// Alternate names supported by __builtin_cpu_is and target multiversioning.
X86_CPU_TYPE_ALIAS(INTEL_BONNELL, "atom")
X86_CPU_TYPE_ALIAS(AMDFAM10H, "amdfam10")
X86_CPU_TYPE_ALIAS(AMDFAM15H, "amdfam15")
X86_CPU_TYPE_ALIAS(AMDFAM1AH, "amdfam1a")
X86_CPU_TYPE_ALIAS(INTEL_SILVERMONT, "slm")

#undef X86_CPU_TYPE_ALIAS
Expand Down Expand Up @@ -104,6 +106,7 @@ X86_CPU_SUBTYPE(INTEL_COREI7_GRANITERAPIDS_D,"graniterapids-d")
X86_CPU_SUBTYPE(INTEL_COREI7_ARROWLAKE, "arrowlake")
X86_CPU_SUBTYPE(INTEL_COREI7_ARROWLAKE_S, "arrowlake-s")
X86_CPU_SUBTYPE(INTEL_COREI7_PANTHERLAKE, "pantherlake")
X86_CPU_SUBTYPE(AMDFAM1AH_ZNVER5, "znver5")

// Alternate names supported by __builtin_cpu_is and target multiversioning.
X86_CPU_SUBTYPE_ALIAS(INTEL_COREI7_ALDERLAKE, "raptorlake")
Expand Down
1 change: 1 addition & 0 deletions llvm/include/llvm/TargetParser/X86TargetParser.h
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Expand Up @@ -142,6 +142,7 @@ enum CPUKind {
CK_ZNVER2,
CK_ZNVER3,
CK_ZNVER4,
CK_ZNVER5,
CK_x86_64,
CK_x86_64_v2,
CK_x86_64_v3,
Expand Down
15 changes: 15 additions & 0 deletions llvm/lib/Target/X86/X86.td
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Expand Up @@ -1549,6 +1549,19 @@ def ProcessorFeatures {
FeatureVPOPCNTDQ];
list<SubtargetFeature> ZN4Features =
!listconcat(ZN3Features, ZN4AdditionalFeatures);


list<SubtargetFeature> ZN5Tuning = ZN4Tuning;
list<SubtargetFeature> ZN5AdditionalFeatures = [FeatureVNNI,
FeatureMOVDIRI,
FeatureMOVDIR64B,
FeatureVP2INTERSECT,
FeaturePREFETCHI,
FeatureAVXVNNI
];
list<SubtargetFeature> ZN5Features =
!listconcat(ZN4Features, ZN5AdditionalFeatures);

}

//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -1898,6 +1911,8 @@ def : ProcModel<"znver3", Znver3Model, ProcessorFeatures.ZN3Features,
ProcessorFeatures.ZN3Tuning>;
def : ProcModel<"znver4", Znver4Model, ProcessorFeatures.ZN4Features,
ProcessorFeatures.ZN4Tuning>;
def : ProcModel<"znver5", Znver4Model, ProcessorFeatures.ZN5Features,
ProcessorFeatures.ZN5Tuning>;

def : Proc<"geode", [FeatureX87, FeatureCX8, FeatureMMX, FeaturePRFCHW],
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/X86/X86PfmCounters.td
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Expand Up @@ -350,3 +350,4 @@ def ZnVer4PfmCounters : ProcPfmCounters {
let ValidationCounters = DefaultAMDPfmValidationCounters;
}
def : PfmCountersBinding<"znver4", ZnVer4PfmCounters>;
def : PfmCountersBinding<"znver5", ZnVer4PfmCounters>;
19 changes: 19 additions & 0 deletions llvm/lib/TargetParser/Host.cpp
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Expand Up @@ -1151,6 +1151,25 @@ static const char *getAMDProcessorTypeAndSubtype(unsigned Family,
break; // "znver4"
}
break; // family 19h
case 26:
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Can you bump the equivalent code in compiler-rt too?

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Will do!

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I posted some patches a while ago to start unifying things so that there's a single canonical version that gets copied and pasted, but those have been stalled for a while on reviewers, so for now we're mostly stuck with the ad-hoc way of doing things.

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I posted some patches a while ago to start unifying things so that there's a single canonical version that gets copied and pasted, but those have been stalled for a while on reviewers, so for now we're mostly stuck with the ad-hoc way of doing things.

Can you point me to those pull requests.
BTW, I see that the compiler-rt change is in place. Do you find any issues there? I think the ordering with respect to libgcc is also okay.
b68bcc1#diff-f0c447f4acaa87cede210a02796f8a3b2f08f6d8acaf951ed4c65465bf37c967

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Oh, looks like I missed it. Sorry about that!

There's #97856, #97861, and #97872 (still a draft).

I want to try and land some test infrastructure first (#101927) so I can ensure the refactorings don't break anything though. There are some more patches that I need to finish doing, but haven't gotten to the rest yet given the current ones are stalled.

CPU = "znver5";
*Type = X86::AMDFAM1AH;
if (Model <= 0x77) {
// Models 00h-0Fh (Breithorn).
// Models 10h-1Fh (Breithorn-Dense).
// Models 20h-2Fh (Strix 1).
// Models 30h-37h (Strix 2).
// Models 38h-3Fh (Strix 3).
// Models 40h-4Fh (Granite Ridge).
// Models 50h-5Fh (Weisshorn).
// Models 60h-6Fh (Krackan1).
// Models 70h-77h (Sarlak).
CPU = "znver5";
*Subtype = X86::AMDFAM1AH_ZNVER5;
break; // "znver5"
}
break;

default:
break; // Unknown AMD CPU.
}
Expand Down
5 changes: 5 additions & 0 deletions llvm/lib/TargetParser/X86TargetParser.cpp
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Expand Up @@ -238,6 +238,10 @@ static constexpr FeatureBitset FeaturesZNVER4 =
FeatureAVX512BITALG | FeatureAVX512VPOPCNTDQ | FeatureAVX512BF16 |
FeatureGFNI | FeatureSHSTK;

static constexpr FeatureBitset FeaturesZNVER5 =
FeaturesZNVER4 | FeatureAVXVNNI | FeatureMOVDIRI | FeatureMOVDIR64B |
FeatureAVX512VP2INTERSECT | FeaturePREFETCHI | FeatureAVXVNNI;

// D151696 tranplanted Mangling and OnlyForCPUDispatchSpecific from
// X86TargetParser.def to here. They are assigned by following ways:
// 1. Copy the mangling from the original CPU_SPEICIFC MACROs. If no, assign
Expand Down Expand Up @@ -417,6 +421,7 @@ constexpr ProcInfo Processors[] = {
{ {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2, '\0', false },
{ {"znver3"}, CK_ZNVER3, FEATURE_AVX2, FeaturesZNVER3, '\0', false },
{ {"znver4"}, CK_ZNVER4, FEATURE_AVX512VBMI2, FeaturesZNVER4, '\0', false },
{ {"znver5"}, CK_ZNVER5, FEATURE_AVX512VP2INTERSECT, FeaturesZNVER5, '\0', false },
// Generic 64-bit processor.
{ {"x86-64"}, CK_x86_64, FEATURE_SSE2 , FeaturesX86_64, '\0', false },
{ {"x86-64-v2"}, CK_x86_64_v2, FEATURE_SSE4_2 , FeaturesX86_64_V2, '\0', false },
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/X86/bypass-slow-division-64.ll
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; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver2 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver5 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ

; Additional tests for 64-bit divide bypass

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1 change: 1 addition & 0 deletions llvm/test/CodeGen/X86/cmp16.ll
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Expand Up @@ -13,6 +13,7 @@
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver2 | FileCheck %s --check-prefixes=X64,X64-FAST
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3 | FileCheck %s --check-prefixes=X64,X64-FAST
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s --check-prefixes=X64,X64-FAST
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver5 | FileCheck %s --check-prefixes=X64,X64-FAST

define i1 @cmp16_reg_eq_reg(i16 %a0, i16 %a1) {
; X86-GENERIC-LABEL: cmp16_reg_eq_reg:
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/X86/cpus-amd.ll
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Expand Up @@ -29,6 +29,7 @@
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver4 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver5 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty

define void @foo() {
ret void
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