[WebAssembly] Add load and store patterns for V8F16.

[brendandahl]

No description provided.

[llvmbot]

@llvm/pr-subscribers-backend-webassembly

Author: Brendan Dahl (brendandahl)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/108119.diff

3 Files Affected:

• (modified) llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp (+4)
• (modified) llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td (+2-2)
• (modified) llvm/test/CodeGen/WebAssembly/half-precision.ll (+21-1)

diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index 5cc084f3ab1387..5971194a045b98 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -96,6 +96,10 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
       setOperationAction(ISD::STORE, T, Custom);
     }
   }
+  if (Subtarget->hasFP16()) {
+    setOperationAction(ISD::LOAD, MVT::v8f16, Custom);
+    setOperationAction(ISD::STORE, MVT::v8f16, Custom);
+  }
   if (Subtarget->hasReferenceTypes()) {
     // We need custom load and store lowering for both externref, funcref and
     // Other. The MVT::Other here represents tables of reference types.
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
index 9d17d90f530541..9be23dacf75013 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -189,7 +189,7 @@ defm LOAD_V128_A64 :
 }
 
 // Def load patterns from WebAssemblyInstrMemory.td for vector types
-foreach vec = StdVecs in {
+foreach vec = AllVecs in {
 defm : LoadPat<vec.vt, load, "LOAD_V128">;
 }
 
@@ -390,7 +390,7 @@ defm STORE_V128_A64 :
 }
 
 // Def store patterns from WebAssemblyInstrMemory.td for vector types
-foreach vec = StdVecs in {
+foreach vec = AllVecs in {
 defm : StorePat<vec.vt, store, "STORE_V128">;
 }
 
diff --git a/llvm/test/CodeGen/WebAssembly/half-precision.ll b/llvm/test/CodeGen/WebAssembly/half-precision.ll
index c0b14d2064d5eb..185b86488747d0 100644
--- a/llvm/test/CodeGen/WebAssembly/half-precision.ll
+++ b/llvm/test/CodeGen/WebAssembly/half-precision.ll
@@ -1,5 +1,4 @@
 ; RUN: llc < %s --mtriple=wasm32-unknown-unknown -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+fp16,+simd128 | FileCheck %s
-; RUN: llc < %s --mtriple=wasm64-unknown-unknown -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+fp16,+simd128 | FileCheck %s
 
 declare float @llvm.wasm.loadf32.f16(ptr)
 declare void @llvm.wasm.storef16.f32(float, ptr)
@@ -308,3 +307,24 @@ define <8 x i16> @trunc_sat_u_v8i16_sat(<8 x half> %x) {
   %a = call <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half> %x)
   ret <8 x i16> %a
 }
+
+; ==============================================================================
+; Load and Store
+; ==============================================================================
+define <8 x half> @load_v8f16(ptr %p) {
+; CHECK-LABEL: load_v8f16:
+; CHECK:         .functype load_v8f16 (i32) -> (v128)
+; CHECK-NEXT:    v128.load $push0=, 0($0)
+; CHECK-NEXT:    return $pop0
+  %v = load <8 x half>, ptr %p
+  ret <8 x half> %v
+}
+
+define void @store_v8f16(<8 x half> %v, ptr %p) {
+; CHECK-LABEL: store_v8f16:
+; CHECK:         .functype store_v8f16 (v128, i32) -> ()
+; CHECK-NEXT:    v128.store 0($1), $0
+; CHECK-NEXT:    return
+  store <8 x half> %v , ptr %p
+  ret void
+}