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[RISCV] Rename XCValu cv.slet(u) to cv.sle(u). #108481

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Merged
merged 1 commit into from
Sep 13, 2024
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[RISCV] Rename XCValu cv.slet(u) to cv.sle(u). #108481

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12 changes: 8 additions & 4 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
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Original file line number Diff line number Diff line change
Expand Up @@ -203,9 +203,9 @@ let Predicates = [HasVendorXCValu, IsRV32],
// General ALU Operations
def CV_ABS : CVInstAluR<0b0101000, 0b011, "cv.abs">,
Sched<[]>;
def CV_SLET : CVInstAluRR<0b0101001, 0b011, "cv.slet">,
def CV_SLE : CVInstAluRR<0b0101001, 0b011, "cv.sle">,
Sched<[]>;
def CV_SLETU : CVInstAluRR<0b0101010, 0b011, "cv.sletu">,
def CV_SLEU : CVInstAluRR<0b0101010, 0b011, "cv.sleu">,
Sched<[]>;
def CV_MIN : CVInstAluRR<0b0101011, 0b011, "cv.min">,
Sched<[]>;
Expand Down Expand Up @@ -276,6 +276,10 @@ let Predicates = [HasVendorXCValu, IsRV32],
// hasSideEffects = 0, mayLoad = 0, mayStore = 0,
// Constraints = "$rd = $rd_wb"

let Predicates = [HasVendorXCValu, IsRV32] in {
def : MnemonicAlias<"cv.slet", "cv.sle">;
def : MnemonicAlias<"cv.sletu", "cv.sleu">;
}

class CVInstSIMDRR<bits<5> funct5, bit F, bit funct1, bits<3> funct3,
RISCVOpcode opcode, dag outs,
Expand Down Expand Up @@ -778,8 +782,8 @@ multiclass PatCoreVAluGprGprImm<Intrinsic intr> {

let Predicates = [HasVendorXCValu, IsRV32], AddedComplexity = 1 in {
def : PatGpr<abs, CV_ABS>;
def : PatGprGpr<setle, CV_SLET>;
def : PatGprGpr<setule, CV_SLETU>;
def : PatGprGpr<setle, CV_SLE>;
def : PatGprGpr<setule, CV_SLEU>;
def : PatGprGpr<smin, CV_MIN>;
def : PatGprGpr<umin, CV_MINU>;
def : PatGprGpr<smax, CV_MAX>;
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/xcvalu.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,7 @@ define i32 @abs(i32 %a) {
define i1 @slet(i32 %a, i32 %b) {
; CHECK-LABEL: slet:
; CHECK: # %bb.0:
; CHECK-NEXT: cv.slet a0, a0, a1
; CHECK-NEXT: cv.sle a0, a0, a1
; CHECK-NEXT: ret
%1 = icmp sle i32 %a, %b
ret i1 %1
Expand All @@ -29,7 +29,7 @@ define i1 @slet(i32 %a, i32 %b) {
define i1 @sletu(i32 %a, i32 %b) {
; CHECK-LABEL: sletu:
; CHECK: # %bb.0:
; CHECK-NEXT: cv.sletu a0, a0, a1
; CHECK-NEXT: cv.sleu a0, a0, a1
; CHECK-NEXT: ret
%1 = icmp ule i32 %a, %b
ret i1 %1
Expand Down
32 changes: 26 additions & 6 deletions llvm/test/MC/RISCV/corev/XCValu-valid.s
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Original file line number Diff line number Diff line change
Expand Up @@ -36,15 +36,25 @@ cv.subrnr a0, a1, a2
# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x8c]
# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}

cv.sle t0, t1, t2
# CHECK-INSTR: cv.sle t0, t1, t2
# CHECK-ENCODING: [0xab,0x32,0x73,0x52]
# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}

cv.slet t0, t1, t2
# CHECK-INSTR: cv.slet t0, t1, t2
# CHECK-INSTR: cv.sle t0, t1, t2
# CHECK-ENCODING: [0xab,0x32,0x73,0x52]
# CHECK-NO-EXT: unrecognized instruction mnemonic

cv.sle a0, a1, a2
# CHECK-INSTR: cv.sle a0, a1, a2
# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x52]
# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}

cv.slet a0, a1, a2
# CHECK-INSTR: cv.slet a0, a1, a2
# CHECK-INSTR: cv.sle a0, a1, a2
# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x52]
# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
# CHECK-NO-EXT: unrecognized instruction mnemonic

cv.subrn t0, t1, t2, 0
# CHECK-INSTR: cv.subrn t0, t1, t2, 0
Expand Down Expand Up @@ -261,15 +271,25 @@ cv.extbs a0, a1
# CHECK-ENCODING: [0x2b,0xb5,0x05,0x64]
# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}

cv.sleu t0, t1, t2
# CHECK-INSTR: cv.sleu t0, t1, t2
# CHECK-ENCODING: [0xab,0x32,0x73,0x54]
# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}

cv.sletu t0, t1, t2
# CHECK-INSTR: cv.sletu t0, t1, t2
# CHECK-INSTR: cv.sleu t0, t1, t2
# CHECK-ENCODING: [0xab,0x32,0x73,0x54]
# CHECK-NO-EXT: unrecognized instruction mnemonic

cv.sleu a0, a1, a2
# CHECK-INSTR: cv.sleu a0, a1, a2
# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x54]
# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}

cv.sletu a0, a1, a2
# CHECK-INSTR: cv.sletu a0, a1, a2
# CHECK-INSTR: cv.sleu a0, a1, a2
# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x54]
# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
# CHECK-NO-EXT: unrecognized instruction mnemonic

cv.min t0, t1, t2
# CHECK-INSTR: cv.min t0, t1, t2
Expand Down
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