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[X86] Add missing immediate qualifier to the (V)INSERTPS instruction names #108568

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Merged
merged 2 commits into from
Sep 15, 2024
Merged

[X86] Add missing immediate qualifier to the (V)INSERTPS instruction names #108568

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4a0ca20
[X86] Add missing immediate qualifier to the (V)INSERTPS instruction …
RKSimon Sep 13, 2024
778f106
Fix tests
RKSimon Sep 13, 2024
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12 changes: 6 additions & 6 deletions llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -703,14 +703,14 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
DestName = getRegName(MI->getOperand(0).getReg());
break;

case X86::INSERTPSrr:
case X86::VINSERTPSrr:
case X86::VINSERTPSZrr:
case X86::INSERTPSrri:
case X86::VINSERTPSrri:
case X86::VINSERTPSZrri:
Src2Name = getRegName(MI->getOperand(2).getReg());
[[fallthrough]];
case X86::INSERTPSrm:
case X86::VINSERTPSrm:
case X86::VINSERTPSZrm:
case X86::INSERTPSrmi:
case X86::VINSERTPSrmi:
case X86::VINSERTPSZrmi:
DestName = getRegName(MI->getOperand(0).getReg());
Src1Name = getRegName(MI->getOperand(1).getReg());
if (MI->getOperand(NumOperands - 1).isImm())
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/X86/X86InstrAVX512.td
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Expand Up @@ -649,12 +649,12 @@ defm : vinsert_for_mask_cast<"VINSERTI64x4Z", v32i8x_info, v64i8_info,
// vinsertps - insert f32 to XMM
let ExeDomain = SSEPackedSingle in {
let isCommutable = 1 in
def VINSERTPSZrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
def VINSERTPSZrri : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
(ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
"vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
[(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, timm:$src3))]>,
EVEX, VVVV, Sched<[SchedWriteFShuffle.XMM]>;
def VINSERTPSZrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
def VINSERTPSZrmi : AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
(ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
"vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
[(set VR128X:$dst, (X86insertps VR128X:$src1,
Expand Down
20 changes: 10 additions & 10 deletions llvm/lib/Target/X86/X86InstrInfo.cpp
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Expand Up @@ -2424,9 +2424,9 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
WorkingMI->getOperand(3).setImm(Mask ^ Imm);
break;
}
case X86::INSERTPSrr:
case X86::VINSERTPSrr:
case X86::VINSERTPSZrr: {
case X86::INSERTPSrri:
case X86::VINSERTPSrri:
case X86::VINSERTPSZrri: {
unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
unsigned ZMask = Imm & 15;
unsigned DstIdx = (Imm >> 4) & 3;
Expand Down Expand Up @@ -7274,9 +7274,9 @@ MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
unsigned Size, Align Alignment) const {
switch (MI.getOpcode()) {
case X86::INSERTPSrr:
case X86::VINSERTPSrr:
case X86::VINSERTPSZrr:
case X86::INSERTPSrri:
case X86::VINSERTPSrri:
case X86::VINSERTPSZrri:
// Attempt to convert the load of inserted vector into a fold load
// of a single float.
if (OpNum == 2) {
Expand All @@ -7289,13 +7289,13 @@ MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
if ((Size == 0 || Size >= 16) && RCSize >= 16 &&
(MI.getOpcode() != X86::INSERTPSrr || Alignment >= Align(4))) {
(MI.getOpcode() != X86::INSERTPSrri || Alignment >= Align(4))) {
int PtrOffset = SrcIdx * 4;
unsigned NewImm = (DstIdx << 4) | ZMask;
unsigned NewOpCode =
(MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm
: (MI.getOpcode() == X86::VINSERTPSrr) ? X86::VINSERTPSrm
: X86::INSERTPSrm;
(MI.getOpcode() == X86::VINSERTPSZrri) ? X86::VINSERTPSZrmi
: (MI.getOpcode() == X86::VINSERTPSrri) ? X86::VINSERTPSrmi
: X86::INSERTPSrmi;
MachineInstr *NewMI =
fuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/X86/X86InstrSSE.td
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Expand Up @@ -5447,7 +5447,7 @@ let Constraints = "$src1 = $dst" in
// in the target vector.
multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
let isCommutable = 1 in
def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, u8imm:$src3),
!if(Is2Addr,
!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Expand All @@ -5456,7 +5456,7 @@ multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
[(set VR128:$dst,
(X86insertps VR128:$src1, VR128:$src2, timm:$src3))]>,
Sched<[SchedWriteFShuffle.XMM]>;
def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, f32mem:$src2, u8imm:$src3),
!if(Is2Addr,
!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/X86/evex-to-vex-compress.mir
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Expand Up @@ -2304,10 +2304,10 @@ body: |
VEXTRACTPSZmr $rdi, 1, $noreg, 0, $noreg, $xmm0, 1
; CHECK: $eax = VEXTRACTPSrr $xmm0, 1
$eax = VEXTRACTPSZrr $xmm0, 1
; CHECK: $xmm0 = VINSERTPSrm $xmm0, $rdi, 1, $noreg, 0, $noreg, 1
$xmm0 = VINSERTPSZrm $xmm0, $rdi, 1, $noreg, 0, $noreg, 1
; CHECK: $xmm0 = VINSERTPSrr $xmm0, $xmm0, 1
$xmm0 = VINSERTPSZrr $xmm0, $xmm0, 1
; CHECK: $xmm0 = VINSERTPSrmi $xmm0, $rdi, 1, $noreg, 0, $noreg, 1
$xmm0 = VINSERTPSZrmi $xmm0, $rdi, 1, $noreg, 0, $noreg, 1
; CHECK: $xmm0 = VINSERTPSrri $xmm0, $xmm0, 1
$xmm0 = VINSERTPSZrri $xmm0, $xmm0, 1
; CHECK: $xmm0 = VROUNDSDmi $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
$xmm0 = VRNDSCALESDZm $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
; CHECK: $xmm0 = VROUNDSDri $xmm0, $xmm1, 15, implicit $mxcsr
Expand Down Expand Up @@ -4072,10 +4072,10 @@ body: |
VEXTRACTPSZmr $rdi, 1, $noreg, 0, $noreg, $xmm16, 1
; CHECK: $eax = VEXTRACTPSZrr $xmm16, 1
$eax = VEXTRACTPSZrr $xmm16, 1
; CHECK: $xmm16 = VINSERTPSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, 1
$xmm16 = VINSERTPSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, 1
; CHECK: $xmm16 = VINSERTPSZrr $xmm16, $xmm16, 1
$xmm16 = VINSERTPSZrr $xmm16, $xmm16, 1
; CHECK: $xmm16 = VINSERTPSZrmi $xmm16, $rdi, 1, $noreg, 0, $noreg, 1
$xmm16 = VINSERTPSZrmi $xmm16, $rdi, 1, $noreg, 0, $noreg, 1
; CHECK: $xmm16 = VINSERTPSZrri $xmm16, $xmm16, 1
$xmm16 = VINSERTPSZrri $xmm16, $xmm16, 1
; CHECK: $xmm16 = VRNDSCALEPDZ128rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
$xmm16 = VRNDSCALEPDZ128rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
; CHECK: $xmm16 = VRNDSCALEPDZ128rri $xmm16, 15, implicit $mxcsr
Expand Down
14 changes: 7 additions & 7 deletions llvm/utils/TableGen/X86ManualFoldTables.def
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Expand Up @@ -215,18 +215,18 @@ NOFOLD(UD1Wr)
// Exclude these two b/c they would conflict with {MMX_MOVD64from64rr, MMX_MOVQ64mr} in unfolding table
NOFOLD(MMX_MOVQ64rr)
NOFOLD(MMX_MOVQ64rr_REV)
// INSERTPSrm has no count_s while INSERTPSrr has count_s.
// INSERTPSrmi has no count_s while INSERTPSrri has count_s.
// count_s is to indicate which element in dst vector is inserted.
// if count_s!=0, we can not fold INSERTPSrr into INSERTPSrm
// if count_s!=0, we can not fold INSERTPSrri into INSERTPSrmi
//
// the following folding can happen when count_s==0
// load xmm0, m32
// insertpsrr xmm1, xmm0, imm
// INSERTPSrri xmm1, xmm0, imm
// =>
// insertpsrm xmm1, m32, imm
NOFOLD(INSERTPSrr)
NOFOLD(VINSERTPSZrr)
NOFOLD(VINSERTPSrr)
// INSERTPSrmi xmm1, m32, imm
NOFOLD(INSERTPSrri)
NOFOLD(VINSERTPSZrri)
NOFOLD(VINSERTPSrri)
// Memory faults are suppressed for CFCMOV with memory operand.
NOFOLD(CFCMOV16rr_REV)
NOFOLD(CFCMOV32rr_REV)
Expand Down
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