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[InitUndef] Also handle inline asm #108951

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Merged
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Sep 19, 2024
Merged

[InitUndef] Also handle inline asm #108951

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16014fe
[InitUndef] Also handle inline asm
nikic Sep 17, 2024
05a7305
Add ARM inline asm test
nikic Sep 18, 2024
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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/InitUndef.cpp
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Expand Up @@ -98,7 +98,7 @@ INITIALIZE_PASS(InitUndef, DEBUG_TYPE, INIT_UNDEF_NAME, false, false)
char &llvm::InitUndefID = InitUndef::ID;

static bool isEarlyClobberMI(MachineInstr &MI) {
return llvm::any_of(MI.defs(), [](const MachineOperand &DefMO) {
return llvm::any_of(MI.all_defs(), [](const MachineOperand &DefMO) {
return DefMO.isReg() && DefMO.isEarlyClobber();
});
}
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13 changes: 13 additions & 0 deletions llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
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Expand Up @@ -364,6 +364,19 @@ define dso_local i32 @test_stxp_undef(ptr %p, i64 %x) nounwind {
ret i32 %res
}

; Same as previous test, but using inline asm.
define dso_local i32 @test_stxp_undef_inline_asm(ptr %p, i64 %x) nounwind {
; CHECK-LABEL: test_stxp_undef_inline_asm:
; CHECK: // %bb.0:
; CHECK-NEXT: //APP
; CHECK-NEXT: stxp w8, x9, x1, [x0]
; CHECK-NEXT: //NO_APP
; CHECK-NEXT: mov w0, w8
; CHECK-NEXT: ret
%res = call i32 asm sideeffect "stxp ${0:w}, ${2}, ${3}, [${1}]", "=&r,r,r,r,~{memory}"(ptr %p, i64 undef, i64 %x)
ret i32 %res
}

declare i32 @llvm.aarch64.stlxr.p0(i64, ptr) nounwind
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; FALLBACK: {{.*}}
13 changes: 13 additions & 0 deletions llvm/test/CodeGen/Thumb2/mve-intrinsics/vcaddq.ll
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Expand Up @@ -710,6 +710,19 @@ entry:
ret <4 x i32> %0
}

define arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_s32_undef_inline_asm() {
; CHECK-LABEL: test_vhcaddq_rot270_s32_undef_inline_asm:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @APP
; CHECK-NEXT: vhcadd.s32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}, #270
; CHECK-NOT: vhcadd.s32 q[[REG:[0-9]+]], q{{[0-9]+}}, q[[REG]], #270
; CHECK-NEXT: @NO_APP
; CHECK-NEXT: bx lr
entry:
%0 = call <4 x i32> asm sideeffect "vhcadd.s32 ${0}, ${1}, ${2}, #270", "=&w,w,w,~{memory}"(<4 x i32> undef, <4 x i32> undef)
ret <4 x i32> %0
}

define arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_x_s8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vhcaddq_rot90_x_s8:
; CHECK: @ %bb.0: @ %entry
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