Skip to content

ValueTracking: simplify udiv/urem recurrences #108973

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 3 commits into from
Nov 7, 2024
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
26 changes: 19 additions & 7 deletions llvm/lib/Analysis/ValueTracking.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1426,16 +1426,23 @@ static void computeKnownBitsFromOperator(const Operator *I,
// this is sufficient to catch some interesting cases.
unsigned Opcode = BO->getOpcode();

// If this is a shift recurrence, we know the bits being shifted in.
// We can combine that with information about the start value of the
// recurrence to conclude facts about the result.
switch (Opcode) {
// If this is a shift recurrence, we know the bits being shifted in. We
// can combine that with information about the start value of the
// recurrence to conclude facts about the result. If this is a udiv
// recurrence, we know that the result can never exceed either the
// numerator or the start value, whichever is greater.
case Instruction::LShr:
case Instruction::AShr:
case Instruction::Shl: {
case Instruction::Shl:
case Instruction::UDiv:
if (BO->getOperand(0) != I)
break;
[[fallthrough]];

// For a urem recurrence, the result can never exceed the start value. The
// phi could either be the numerator or the denominator.
case Instruction::URem: {
// We have matched a recurrence of the form:
// %iv = [R, %entry], [%iv.next, %backedge]
// %iv.next = shift_op %iv, L
Expand All @@ -1453,8 +1460,10 @@ static void computeKnownBitsFromOperator(const Operator *I,
Known.Zero.setLowBits(Known2.countMinTrailingZeros());
break;
case Instruction::LShr:
// A lshr recurrence will preserve the leading zeros of the
// start value
case Instruction::UDiv:
case Instruction::URem:
// lshr, udiv, and urem recurrences will preserve the leading zeros of
// the start value.
Known.Zero.setHighBits(Known2.countMinLeadingZeros());
break;
case Instruction::AShr:
Expand Down Expand Up @@ -1542,6 +1551,7 @@ static void computeKnownBitsFromOperator(const Operator *I,
}
break;
}

default:
break;
}
Expand Down Expand Up @@ -9039,12 +9049,14 @@ bool llvm::matchSimpleRecurrence(const PHINode *P, BinaryOperator *&BO,
switch (Opcode) {
default:
continue;
// TODO: Expand list -- xor, div, gep, uaddo, etc..
// TODO: Expand list -- xor, gep, uadd.sat etc.
case Instruction::LShr:
case Instruction::AShr:
case Instruction::Shl:
case Instruction::Add:
case Instruction::Sub:
case Instruction::UDiv:
case Instruction::URem:
case Instruction::And:
case Instruction::Or:
case Instruction::Mul:
Expand Down
10 changes: 2 additions & 8 deletions llvm/test/Analysis/ValueTracking/recurrence-knownbits.ll
Original file line number Diff line number Diff line change
Expand Up @@ -86,12 +86,9 @@ define i64 @test_udiv(i1 %c) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 9, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[IV_NEXT]] = udiv i64 [[IV]], 3
; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
; CHECK: exit:
; CHECK-NEXT: [[RES:%.*]] = and i64 [[IV]], 16
; CHECK-NEXT: ret i64 [[RES]]
; CHECK-NEXT: ret i64 0
;
entry:
br label %loop
Expand Down Expand Up @@ -132,12 +129,9 @@ define i64 @test_urem(i1 %c) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 3, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[IV_NEXT]] = urem i64 9, [[IV]]
; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
; CHECK: exit:
; CHECK-NEXT: [[RES:%.*]] = and i64 [[IV]], 4
; CHECK-NEXT: ret i64 [[RES]]
; CHECK-NEXT: ret i64 0
;
entry:
br label %loop
Expand Down
Loading