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[LLVM][TableGen] Change DAGISel code to use const RecordKeeper #109038

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Merged
merged 1 commit into from
Sep 18, 2024
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[LLVM][TableGen] Change DAGISel code to use const RecordKeeper #109038

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10 changes: 5 additions & 5 deletions llvm/utils/TableGen/DAGISelEmitter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -25,11 +25,11 @@ namespace {
/// DAGISelEmitter - The top-level class which coordinates construction
/// and emission of the instruction selector.
class DAGISelEmitter {
RecordKeeper &Records; // Just so we can get at the timing functions.
CodeGenDAGPatterns CGP;
const RecordKeeper &Records; // Just so we can get at the timing functions.
const CodeGenDAGPatterns CGP;

public:
explicit DAGISelEmitter(RecordKeeper &R) : Records(R), CGP(R) {}
explicit DAGISelEmitter(const RecordKeeper &R) : Records(R), CGP(R) {}
void run(raw_ostream &OS);
};
} // End anonymous namespace
Expand Down Expand Up @@ -81,8 +81,8 @@ namespace {
// In particular, we want to match maximal patterns first and lowest cost within
// a particular complexity first.
struct PatternSortingPredicate {
PatternSortingPredicate(CodeGenDAGPatterns &cgp) : CGP(cgp) {}
CodeGenDAGPatterns &CGP;
PatternSortingPredicate(const CodeGenDAGPatterns &cgp) : CGP(cgp) {}
const CodeGenDAGPatterns &CGP;

bool operator()(const PatternToMatch *LHS, const PatternToMatch *RHS) {
const TreePatternNode &LT = LHS->getSrcPattern();
Expand Down
20 changes: 10 additions & 10 deletions llvm/utils/TableGen/DAGISelMatcherGen.cpp
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Expand Up @@ -23,7 +23,7 @@ using namespace llvm;
/// getRegisterValueType - Look up and return the ValueType of the specified
/// register. If the register is a member of multiple register classes, they
/// must all have the same type.
static MVT::SimpleValueType getRegisterValueType(Record *R,
static MVT::SimpleValueType getRegisterValueType(const Record *R,
const CodeGenTarget &T) {
bool FoundRC = false;
MVT::SimpleValueType VT = MVT::Other;
Expand Down Expand Up @@ -91,7 +91,7 @@ class MatcherGen {
/// PhysRegInputs - List list has an entry for each explicitly specified
/// physreg input to the pattern. The first elt is the Register node, the
/// second is the recorded slot number the input pattern match saved it in.
SmallVector<std::pair<Record *, unsigned>, 2> PhysRegInputs;
SmallVector<std::pair<const Record *, unsigned>, 2> PhysRegInputs;

/// Matcher - This is the top level of the generated matcher, the result.
Matcher *TheMatcher;
Expand Down Expand Up @@ -220,13 +220,13 @@ void MatcherGen::EmitLeafMatchCode(const TreePatternNode &N) {
return;
}

DefInit *DI = dyn_cast<DefInit>(N.getLeafValue());
const DefInit *DI = dyn_cast<DefInit>(N.getLeafValue());
if (!DI) {
errs() << "Unknown leaf kind: " << N << "\n";
abort();
}

Record *LeafRec = DI->getDef();
const Record *LeafRec = DI->getDef();

// A ValueType leaf node can represent a register when named, or itself when
// unnamed.
Expand Down Expand Up @@ -673,7 +673,7 @@ void MatcherGen::EmitResultLeafAsOperand(const TreePatternNode &N,

// If this is an explicit register reference, handle it.
if (DefInit *DI = dyn_cast<DefInit>(N.getLeafValue())) {
Record *Def = DI->getDef();
const Record *Def = DI->getDef();
if (Def->isSubClassOf("Register")) {
const CodeGenRegister *Reg = CGP.getTargetInfo().getRegBank().getReg(Def);
AddMatcher(new EmitRegisterMatcher(Reg, N.getSimpleType(0)));
Expand All @@ -690,7 +690,7 @@ void MatcherGen::EmitResultLeafAsOperand(const TreePatternNode &N,
if (Def->getName() == "undef_tied_input") {
MVT::SimpleValueType ResultVT = N.getSimpleType(0);
auto IDOperandNo = NextRecordedOperandNo++;
Record *ImpDef = Def->getRecords().getDef("IMPLICIT_DEF");
const Record *ImpDef = Def->getRecords().getDef("IMPLICIT_DEF");
CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(ImpDef);
AddMatcher(new EmitNodeMatcher(II, ResultVT, std::nullopt, false, false,
false, false, -1, IDOperandNo));
Expand Down Expand Up @@ -907,11 +907,11 @@ void MatcherGen::EmitResultInstructionAsOperand(
if (isRoot && !Pattern.getDstRegs().empty()) {
// If the root came from an implicit def in the instruction handling stuff,
// don't re-add it.
Record *HandledReg = nullptr;
const Record *HandledReg = nullptr;
if (II.HasOneImplicitDefWithKnownVT(CGT) != MVT::Other)
HandledReg = II.ImplicitDefs[0];

for (Record *Reg : Pattern.getDstRegs()) {
for (const Record *Reg : Pattern.getDstRegs()) {
if (!Reg->isSubClassOf("Register") || Reg == HandledReg)
continue;
ResultVTs.push_back(getRegisterValueType(Reg, CGT));
Expand Down Expand Up @@ -1042,7 +1042,7 @@ void MatcherGen::EmitResultCode() {
if (!Pattern.getDstRegs().empty()) {
// If the root came from an implicit def in the instruction handling stuff,
// don't re-add it.
Record *HandledReg = nullptr;
const Record *HandledReg = nullptr;
const TreePatternNode &DstPat = Pattern.getDstPattern();
if (!DstPat.isLeaf() && DstPat.getOperator()->isSubClassOf("Instruction")) {
const CodeGenTarget &CGT = CGP.getTargetInfo();
Expand All @@ -1052,7 +1052,7 @@ void MatcherGen::EmitResultCode() {
HandledReg = II.ImplicitDefs[0];
}

for (Record *Reg : Pattern.getDstRegs()) {
for (const Record *Reg : Pattern.getDstRegs()) {
if (!Reg->isSubClassOf("Register") || Reg == HandledReg)
continue;
++NumSrcResults;
Expand Down
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