[CodeGen] Use Register in SwitchLoweringUtils. NFC #109092
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Use an empty Register() instead of -1U.
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@llvm/pr-subscribers-llvm-globalisel Author: Craig Topper (topperc) ChangesUse an empty Register() instead of -1U. Full diff: https://github.com/llvm/llvm-project/pull/109092.diff 5 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/SwitchLoweringUtils.h b/llvm/include/llvm/CodeGen/SwitchLoweringUtils.h
index 9282c4a771afb2..9f1d6f7b4f9524 100644
--- a/llvm/include/llvm/CodeGen/SwitchLoweringUtils.h
+++ b/llvm/include/llvm/CodeGen/SwitchLoweringUtils.h
@@ -170,7 +170,7 @@ struct CaseBlock {
struct JumpTable {
/// The virtual register containing the index of the jump table entry
/// to jump to.
- unsigned Reg;
+ Register Reg;
/// The JumpTableIndex for this jump table in the function.
unsigned JTI;
/// The MBB into which to emit the code for the indirect jump.
@@ -182,7 +182,7 @@ struct JumpTable {
/// The debug location of the instruction this JumpTable was produced from.
std::optional<SDLoc> SL; // For SelectionDAG
- JumpTable(unsigned R, unsigned J, MachineBasicBlock *M, MachineBasicBlock *D,
+ JumpTable(Register R, unsigned J, MachineBasicBlock *M, MachineBasicBlock *D,
std::optional<SDLoc> SL)
: Reg(R), JTI(J), MBB(M), Default(D), SL(SL) {}
};
@@ -218,7 +218,7 @@ struct BitTestBlock {
APInt First;
APInt Range;
const Value *SValue;
- unsigned Reg;
+ Register Reg;
MVT RegVT;
bool Emitted;
bool ContiguousRange;
@@ -229,7 +229,7 @@ struct BitTestBlock {
BranchProbability DefaultProb;
bool FallthroughUnreachable = false;
- BitTestBlock(APInt F, APInt R, const Value *SV, unsigned Rg, MVT RgVT, bool E,
+ BitTestBlock(APInt F, APInt R, const Value *SV, Register Rg, MVT RgVT, bool E,
bool CR, MachineBasicBlock *P, MachineBasicBlock *D,
BitTestInfo C, BranchProbability Pr)
: First(std::move(F)), Range(std::move(R)), SValue(SV), Reg(Rg),
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 5710bda2b2cf86..07c189344c6429 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -838,7 +838,7 @@ void IRTranslator::splitWorkItem(SwitchCG::SwitchWorkList &WorkList,
void IRTranslator::emitJumpTable(SwitchCG::JumpTable &JT,
MachineBasicBlock *MBB) {
// Emit the code for the jump table
- assert(JT.Reg != -1U && "Should lower JT Header first!");
+ assert(JT.Reg && "Should lower JT Header first!");
MachineIRBuilder MIB(*MBB->getParent());
MIB.setMBB(*MBB);
MIB.setDebugLoc(CurBuilder->getDebugLoc());
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index a719ff859e778e..eec89f04c6356d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -2981,7 +2981,7 @@ void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
void SelectionDAGBuilder::visitJumpTable(SwitchCG::JumpTable &JT) {
// Emit the code for the jump table
assert(JT.SL && "Should set SDLoc for SelectionDAG!");
- assert(JT.Reg != -1U && "Should lower JT Header first!");
+ assert(JT.Reg && "Should lower JT Header first!");
EVT PTy = DAG.getTargetLoweringInfo().getJumpTableRegTy(DAG.getDataLayout());
SDValue Index = DAG.getCopyFromReg(getControlRoot(), *JT.SL, JT.Reg, PTy);
SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
@@ -3261,10 +3261,9 @@ void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
/// visitBitTestCase - this function produces one "bit test"
void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
- MachineBasicBlock* NextMBB,
+ MachineBasicBlock *NextMBB,
BranchProbability BranchProbToNext,
- unsigned Reg,
- BitTestCase &B,
+ Register Reg, BitTestCase &B,
MachineBasicBlock *SwitchBB) {
SDLoc dl = getCurSDLoc();
MVT VT = BB.RegVT;
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
index 9544f02b9a4808..3f8a3e7ffb65bb 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
@@ -526,7 +526,7 @@ class SelectionDAGBuilder {
void visitBitTestHeader(SwitchCG::BitTestBlock &B,
MachineBasicBlock *SwitchBB);
void visitBitTestCase(SwitchCG::BitTestBlock &BB, MachineBasicBlock *NextMBB,
- BranchProbability BranchProbToNext, unsigned Reg,
+ BranchProbability BranchProbToNext, Register Reg,
SwitchCG::BitTestCase &B, MachineBasicBlock *SwitchBB);
void visitJumpTable(SwitchCG::JumpTable &JT);
void visitJumpTableHeader(SwitchCG::JumpTable &JT,
diff --git a/llvm/lib/CodeGen/SwitchLoweringUtils.cpp b/llvm/lib/CodeGen/SwitchLoweringUtils.cpp
index e741a0fc49fb3d..038c499fe236e0 100644
--- a/llvm/lib/CodeGen/SwitchLoweringUtils.cpp
+++ b/llvm/lib/CodeGen/SwitchLoweringUtils.cpp
@@ -254,7 +254,7 @@ bool SwitchCG::SwitchLowering::buildJumpTable(const CaseClusterVector &Clusters,
->createJumpTableIndex(Table);
// Set up the jump table info.
- JumpTable JT(-1U, JTI, JumpTableMBB, nullptr, SL);
+ JumpTable JT(Register(), JTI, JumpTableMBB, nullptr, SL);
JumpTableHeader JTH(Clusters[First].Low->getValue(),
Clusters[Last].High->getValue(), SI->getCondition(),
nullptr, false);
@@ -455,7 +455,7 @@ bool SwitchCG::SwitchLowering::buildBitTests(CaseClusterVector &Clusters,
BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraProb));
}
BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
- SI->getCondition(), -1U, MVT::Other, false,
+ SI->getCondition(), Register(), MVT::Other, false,
ContiguousRange, nullptr, nullptr, std::move(BTI),
TotalProb);
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@llvm/pr-subscribers-llvm-selectiondag Author: Craig Topper (topperc) ChangesUse an empty Register() instead of -1U. Full diff: https://github.com/llvm/llvm-project/pull/109092.diff 5 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/SwitchLoweringUtils.h b/llvm/include/llvm/CodeGen/SwitchLoweringUtils.h
index 9282c4a771afb2..9f1d6f7b4f9524 100644
--- a/llvm/include/llvm/CodeGen/SwitchLoweringUtils.h
+++ b/llvm/include/llvm/CodeGen/SwitchLoweringUtils.h
@@ -170,7 +170,7 @@ struct CaseBlock {
struct JumpTable {
/// The virtual register containing the index of the jump table entry
/// to jump to.
- unsigned Reg;
+ Register Reg;
/// The JumpTableIndex for this jump table in the function.
unsigned JTI;
/// The MBB into which to emit the code for the indirect jump.
@@ -182,7 +182,7 @@ struct JumpTable {
/// The debug location of the instruction this JumpTable was produced from.
std::optional<SDLoc> SL; // For SelectionDAG
- JumpTable(unsigned R, unsigned J, MachineBasicBlock *M, MachineBasicBlock *D,
+ JumpTable(Register R, unsigned J, MachineBasicBlock *M, MachineBasicBlock *D,
std::optional<SDLoc> SL)
: Reg(R), JTI(J), MBB(M), Default(D), SL(SL) {}
};
@@ -218,7 +218,7 @@ struct BitTestBlock {
APInt First;
APInt Range;
const Value *SValue;
- unsigned Reg;
+ Register Reg;
MVT RegVT;
bool Emitted;
bool ContiguousRange;
@@ -229,7 +229,7 @@ struct BitTestBlock {
BranchProbability DefaultProb;
bool FallthroughUnreachable = false;
- BitTestBlock(APInt F, APInt R, const Value *SV, unsigned Rg, MVT RgVT, bool E,
+ BitTestBlock(APInt F, APInt R, const Value *SV, Register Rg, MVT RgVT, bool E,
bool CR, MachineBasicBlock *P, MachineBasicBlock *D,
BitTestInfo C, BranchProbability Pr)
: First(std::move(F)), Range(std::move(R)), SValue(SV), Reg(Rg),
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 5710bda2b2cf86..07c189344c6429 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -838,7 +838,7 @@ void IRTranslator::splitWorkItem(SwitchCG::SwitchWorkList &WorkList,
void IRTranslator::emitJumpTable(SwitchCG::JumpTable &JT,
MachineBasicBlock *MBB) {
// Emit the code for the jump table
- assert(JT.Reg != -1U && "Should lower JT Header first!");
+ assert(JT.Reg && "Should lower JT Header first!");
MachineIRBuilder MIB(*MBB->getParent());
MIB.setMBB(*MBB);
MIB.setDebugLoc(CurBuilder->getDebugLoc());
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index a719ff859e778e..eec89f04c6356d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -2981,7 +2981,7 @@ void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
void SelectionDAGBuilder::visitJumpTable(SwitchCG::JumpTable &JT) {
// Emit the code for the jump table
assert(JT.SL && "Should set SDLoc for SelectionDAG!");
- assert(JT.Reg != -1U && "Should lower JT Header first!");
+ assert(JT.Reg && "Should lower JT Header first!");
EVT PTy = DAG.getTargetLoweringInfo().getJumpTableRegTy(DAG.getDataLayout());
SDValue Index = DAG.getCopyFromReg(getControlRoot(), *JT.SL, JT.Reg, PTy);
SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
@@ -3261,10 +3261,9 @@ void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
/// visitBitTestCase - this function produces one "bit test"
void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
- MachineBasicBlock* NextMBB,
+ MachineBasicBlock *NextMBB,
BranchProbability BranchProbToNext,
- unsigned Reg,
- BitTestCase &B,
+ Register Reg, BitTestCase &B,
MachineBasicBlock *SwitchBB) {
SDLoc dl = getCurSDLoc();
MVT VT = BB.RegVT;
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
index 9544f02b9a4808..3f8a3e7ffb65bb 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
@@ -526,7 +526,7 @@ class SelectionDAGBuilder {
void visitBitTestHeader(SwitchCG::BitTestBlock &B,
MachineBasicBlock *SwitchBB);
void visitBitTestCase(SwitchCG::BitTestBlock &BB, MachineBasicBlock *NextMBB,
- BranchProbability BranchProbToNext, unsigned Reg,
+ BranchProbability BranchProbToNext, Register Reg,
SwitchCG::BitTestCase &B, MachineBasicBlock *SwitchBB);
void visitJumpTable(SwitchCG::JumpTable &JT);
void visitJumpTableHeader(SwitchCG::JumpTable &JT,
diff --git a/llvm/lib/CodeGen/SwitchLoweringUtils.cpp b/llvm/lib/CodeGen/SwitchLoweringUtils.cpp
index e741a0fc49fb3d..038c499fe236e0 100644
--- a/llvm/lib/CodeGen/SwitchLoweringUtils.cpp
+++ b/llvm/lib/CodeGen/SwitchLoweringUtils.cpp
@@ -254,7 +254,7 @@ bool SwitchCG::SwitchLowering::buildJumpTable(const CaseClusterVector &Clusters,
->createJumpTableIndex(Table);
// Set up the jump table info.
- JumpTable JT(-1U, JTI, JumpTableMBB, nullptr, SL);
+ JumpTable JT(Register(), JTI, JumpTableMBB, nullptr, SL);
JumpTableHeader JTH(Clusters[First].Low->getValue(),
Clusters[Last].High->getValue(), SI->getCondition(),
nullptr, false);
@@ -455,7 +455,7 @@ bool SwitchCG::SwitchLowering::buildBitTests(CaseClusterVector &Clusters,
BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraProb));
}
BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
- SI->getCondition(), -1U, MVT::Other, false,
+ SI->getCondition(), Register(), MVT::Other, false,
ContiguousRange, nullptr, nullptr, std::move(BTI),
TotalProb);
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arsenm
approved these changes
Sep 18, 2024
tmsri
pushed a commit
to tmsri/llvm-project
that referenced
this pull request
Sep 19, 2024
Use an empty Register() instead of -1U.
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Use an empty Register() instead of -1U.