[LLVM][TableGen] Change InstrInfoEmitter to use const RecordKeeper

llvm/utils/TableGen/Common/CodeGenInstruction.cpp

@@ -485,8 +485,8 @@ CodeGenInstruction::CodeGenInstruction(const Record *R)
   isCodeGenOnly = R->getValueAsBit("isCodeGenOnly");
   isPseudo = R->getValueAsBit("isPseudo");
   isMeta = R->getValueAsBit("isMeta");
-  ImplicitDefs = R->getValueAsListOfDefs("Defs");
-  ImplicitUses = R->getValueAsListOfDefs("Uses");
+  ImplicitDefs = R->getValueAsListOfConstDefs("Defs");
+  ImplicitUses = R->getValueAsListOfConstDefs("Uses");
 
   // This flag is only inferred from the pattern.
   hasChain = false;
@@ -523,7 +523,7 @@ MVT::SimpleValueType CodeGenInstruction::HasOneImplicitDefWithKnownVT(
     return MVT::Other;
 
   // Check to see if the first implicit def has a resolvable type.
-  Record *FirstImplicitDef = ImplicitDefs[0];
+  const Record *FirstImplicitDef = ImplicitDefs[0];
   assert(FirstImplicitDef->isSubClassOf("Register"));
   const std::vector<ValueTypeByHwMode> &RegVTs =
       TargetInfo.getRegisterVTs(FirstImplicitDef);

llvm/utils/TableGen/Common/CodeGenInstruction.h

@@ -235,7 +235,7 @@ class CodeGenInstruction {
 
   /// ImplicitDefs/ImplicitUses - These are lists of registers that are
   /// implicitly defined and used by the instruction.
-  std::vector<Record *> ImplicitDefs, ImplicitUses;
+  std::vector<const Record *> ImplicitDefs, ImplicitUses;
 
   // Various boolean values we track for the instruction.
   bool isPreISelOpcode : 1;

llvm/utils/TableGen/Common/CodeGenTarget.cpp

@@ -234,7 +234,8 @@ CodeGenTarget::getRegisterClass(const Record *R) const {
   return *getRegBank().getRegClass(R);
 }
 
-std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R) const {
+std::vector<ValueTypeByHwMode>
+CodeGenTarget::getRegisterVTs(const Record *R) const {
   const CodeGenRegister *Reg = getRegBank().getReg(R);
   std::vector<ValueTypeByHwMode> Result;
   for (const auto &RC : getRegBank().getRegClasses()) {

llvm/utils/TableGen/Common/CodeGenTarget.h

@@ -144,7 +144,7 @@ class CodeGenTarget {
 
   /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the
   /// specified physical register.
-  std::vector<ValueTypeByHwMode> getRegisterVTs(Record *R) const;
+  std::vector<ValueTypeByHwMode> getRegisterVTs(const Record *R) const;
 
   ArrayRef<ValueTypeByHwMode> getLegalValueTypes() const {
     if (LegalValueTypes.empty())

llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h

@@ -2337,7 +2337,7 @@ class BuildMIAction : public MatchAction {
   const CodeGenInstruction *I;
   InstructionMatcher *Matched;
   std::vector<std::unique_ptr<OperandRenderer>> OperandRenderers;
-  SmallPtrSet<Record *, 4> DeadImplicitDefs;
+  SmallPtrSet<const Record *, 4> DeadImplicitDefs;
 
   std::vector<const InstructionMatcher *> CopiedFlags;
   std::vector<StringRef> SetFlags;
@@ -2365,7 +2365,7 @@ class BuildMIAction : public MatchAction {
 
   void chooseInsnToMutate(RuleMatcher &Rule);
 
-  void setDeadImplicitDef(Record *R) { DeadImplicitDefs.insert(R); }
+  void setDeadImplicitDef(const Record *R) { DeadImplicitDefs.insert(R); }
 
   template <class Kind, class... Args> Kind &addRenderer(Args &&...args) {
     OperandRenderers.emplace_back(

llvm/utils/TableGen/DAGISelMatcherGen.cpp

@@ -23,7 +23,7 @@ using namespace llvm;
 /// getRegisterValueType - Look up and return the ValueType of the specified
 /// register. If the register is a member of multiple register classes, they
 /// must all have the same type.
-static MVT::SimpleValueType getRegisterValueType(Record *R,
+static MVT::SimpleValueType getRegisterValueType(const Record *R,
                                                  const CodeGenTarget &T) {
   bool FoundRC = false;
   MVT::SimpleValueType VT = MVT::Other;
@@ -907,11 +907,11 @@ void MatcherGen::EmitResultInstructionAsOperand(
   if (isRoot && !Pattern.getDstRegs().empty()) {
     // If the root came from an implicit def in the instruction handling stuff,
     // don't re-add it.
-    Record *HandledReg = nullptr;
+    const Record *HandledReg = nullptr;
     if (II.HasOneImplicitDefWithKnownVT(CGT) != MVT::Other)
       HandledReg = II.ImplicitDefs[0];
 
-    for (Record *Reg : Pattern.getDstRegs()) {
+    for (const Record *Reg : Pattern.getDstRegs()) {
       if (!Reg->isSubClassOf("Register") || Reg == HandledReg)
         continue;
       ResultVTs.push_back(getRegisterValueType(Reg, CGT));
@@ -1042,7 +1042,7 @@ void MatcherGen::EmitResultCode() {
   if (!Pattern.getDstRegs().empty()) {
     // If the root came from an implicit def in the instruction handling stuff,
     // don't re-add it.
-    Record *HandledReg = nullptr;
+    const Record *HandledReg = nullptr;
     const TreePatternNode &DstPat = Pattern.getDstPattern();
     if (!DstPat.isLeaf() && DstPat.getOperator()->isSubClassOf("Instruction")) {
       const CodeGenTarget &CGT = CGP.getTargetInfo();

llvm/utils/TableGen/GlobalISelEmitter.cpp

@@ -2368,7 +2368,7 @@ void GlobalISelEmitter::emitRunCustomAction(raw_ostream &OS) {
 }
 
 void GlobalISelEmitter::postProcessRule(RuleMatcher &M) {
-  SmallPtrSet<Record *, 16> UsedRegs;
+  SmallPtrSet<const Record *, 16> UsedRegs;
 
   // TODO: deal with subregs?
   for (auto &A : M.actions()) {

llvm/utils/TableGen/InstrInfoEmitter.cpp

@@ -48,12 +48,12 @@ static cl::opt<bool> ExpandMIOperandInfo(
 namespace {
 
 class InstrInfoEmitter {
-  RecordKeeper &Records;
-  CodeGenDAGPatterns CDP;
+  const RecordKeeper &Records;
+  const CodeGenDAGPatterns CDP;
   const CodeGenSchedModels &SchedModels;
 
 public:
-  InstrInfoEmitter(RecordKeeper &R)
+  InstrInfoEmitter(const RecordKeeper &R)
       : Records(R), CDP(R), SchedModels(CDP.getTargetInfo().getSchedModels()) {}
 
   // run - Output the instruction set description.
@@ -88,8 +88,8 @@ class InstrInfoEmitter {
   /// Write verifyInstructionPredicates methods.
   void emitFeatureVerifier(raw_ostream &OS, const CodeGenTarget &Target);
   void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
-                  Record *InstrInfo,
-                  std::map<std::vector<Record *>, unsigned> &EL,
+                  const Record *InstrInfo,
+                  std::map<std::vector<const Record *>, unsigned> &EL,
                   const OperandInfoMapTy &OperandInfo, raw_ostream &OS);
   void emitOperandTypeMappings(
       raw_ostream &OS, const CodeGenTarget &Target,
@@ -136,7 +136,7 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
     // registers in their multi-operand operands.  It may also be an anonymous
     // operand, which has a single operand, but no declared class for the
     // operand.
-    DagInit *MIOI = Op.MIOperandInfo;
+    const DagInit *MIOI = Op.MIOperandInfo;
 
     if (!MIOI || MIOI->getNumArgs() == 0) {
       // Single, anonymous, operand.
@@ -356,10 +356,11 @@ void InstrInfoEmitter::emitOperandTypeMappings(
     ArrayRef<const CodeGenInstruction *> NumberedInstructions) {
 
   StringRef Namespace = Target.getInstNamespace();
-  std::vector<Record *> Operands = Records.getAllDerivedDefinitions("Operand");
-  std::vector<Record *> RegisterOperands =
+  ArrayRef<const Record *> Operands =
+      Records.getAllDerivedDefinitions("Operand");
+  ArrayRef<const Record *> RegisterOperands =
       Records.getAllDerivedDefinitions("RegisterOperand");
-  std::vector<Record *> RegisterClasses =
+  ArrayRef<const Record *> RegisterClasses =
       Records.getAllDerivedDefinitions("RegisterClass");
 
   OS << "#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
@@ -370,9 +371,9 @@ void InstrInfoEmitter::emitOperandTypeMappings(
   OS << "enum OperandType {\n";
 
   unsigned EnumVal = 0;
-  for (const std::vector<Record *> *RecordsToAdd :
-       {&Operands, &RegisterOperands, &RegisterClasses}) {
-    for (const Record *Op : *RecordsToAdd) {
+  for (ArrayRef<const Record *> RecordsToAdd :
+       {Operands, RegisterOperands, RegisterClasses}) {
+    for (const Record *Op : RecordsToAdd) {
       if (!Op->isAnonymous())
         OS << "  " << Op->getName() << " = " << EnumVal << ",\n";
       ++EnumVal;
@@ -764,8 +765,8 @@ void InstrInfoEmitter::emitFeatureVerifier(raw_ostream &OS,
     }
   }
 
-  llvm::sort(FeatureBitsets, [&](const std::vector<const Record *> &A,
-                                 const std::vector<const Record *> &B) {
+  llvm::sort(FeatureBitsets, [&](ArrayRef<const Record *> A,
+                                 ArrayRef<const Record *> B) {
     if (A.size() < B.size())
       return true;
     if (A.size() > B.size())
@@ -928,9 +929,9 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
   emitSourceFileHeader("Target Instruction Enum Values and Descriptors", OS);
   emitEnums(OS);
 
-  CodeGenTarget &Target = CDP.getTargetInfo();
+  const CodeGenTarget &Target = CDP.getTargetInfo();
   const std::string &TargetName = std::string(Target.getName());
-  Record *InstrInfo = Target.getInstructionSet();
+  const Record *InstrInfo = Target.getInstructionSet();
 
   // Collect all of the operand info records.
   Records.startTimer("Collect operand info");
@@ -941,11 +942,11 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
 
   // Collect all of the instruction's implicit uses and defs.
   Records.startTimer("Collect uses/defs");
-  std::map<std::vector<Record *>, unsigned> EmittedLists;
-  std::vector<std::vector<Record *>> ImplicitLists;
+  std::map<std::vector<const Record *>, unsigned> EmittedLists;
+  std::vector<std::vector<const Record *>> ImplicitLists;
   unsigned ImplicitListSize = 0;
   for (const CodeGenInstruction *II : Target.getInstructionsByEnumValue()) {
-    std::vector<Record *> ImplicitOps = II->ImplicitUses;
+    std::vector<const Record *> ImplicitOps = II->ImplicitUses;
     llvm::append_range(ImplicitOps, II->ImplicitDefs);
     if (EmittedLists.insert({ImplicitOps, ImplicitListSize}).second) {
       ImplicitLists.push_back(ImplicitOps);
@@ -1175,8 +1176,8 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
 }
 
 void InstrInfoEmitter::emitRecord(
-    const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo,
-    std::map<std::vector<Record *>, unsigned> &EmittedLists,
+    const CodeGenInstruction &Inst, unsigned Num, const Record *InstrInfo,
+    std::map<std::vector<const Record *>, unsigned> &EmittedLists,
     const OperandInfoMapTy &OperandInfoMap, raw_ostream &OS) {
   int MinOperands = 0;
   if (!Inst.Operands.empty())
@@ -1195,11 +1196,11 @@ void InstrInfoEmitter::emitRecord(
      << Inst.TheDef->getValueAsInt("Size") << ",\t"
      << SchedModels.getSchedClassIdx(Inst) << ",\t";
 
-  CodeGenTarget &Target = CDP.getTargetInfo();
+  const CodeGenTarget &Target = CDP.getTargetInfo();
 
   // Emit the implicit use/def list...
   OS << Inst.ImplicitUses.size() << ",\t" << Inst.ImplicitDefs.size() << ",\t";
-  std::vector<Record *> ImplicitOps = Inst.ImplicitUses;
+  std::vector<const Record *> ImplicitOps = Inst.ImplicitUses;
   llvm::append_range(ImplicitOps, Inst.ImplicitDefs);
   OS << Target.getName() << "ImpOpBase + " << EmittedLists[ImplicitOps]
      << ",\t";