[RISCV] Move the rest of Zfa FLI instruction handling to lowerConstantFP. #109217
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
…tFP. We already moved the fneg case. This moves the rest so we can drop the custom isel.
|
@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesWe already moved the fneg case. This moves the rest so we can drop the custom isel. Full diff: https://github.com/llvm/llvm-project/pull/109217.diff 2 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index f22ab1e5e9d48a..fcd46b5921c4de 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -889,29 +889,6 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
}
case ISD::ConstantFP: {
const APFloat &APF = cast<ConstantFPSDNode>(Node)->getValueAPF();
- int FPImm = static_cast<const RISCVTargetLowering *>(TLI)->getLegalZfaFPImm(
- APF, VT);
- if (FPImm >= 0) {
- unsigned Opc;
- switch (VT.SimpleTy) {
- default:
- llvm_unreachable("Unexpected size");
- case MVT::f16:
- Opc = RISCV::FLI_H;
- break;
- case MVT::f32:
- Opc = RISCV::FLI_S;
- break;
- case MVT::f64:
- Opc = RISCV::FLI_D;
- break;
- }
- SDNode *Res = CurDAG->getMachineNode(
- Opc, DL, VT, CurDAG->getTargetConstant(FPImm, DL, XLenVT));
-
- ReplaceNode(Node, Res);
- return;
- }
bool NegZeroF64 = APF.isNegZero() && VT == MVT::f64;
SDValue Imm;
@@ -3552,13 +3529,6 @@ bool RISCVDAGToDAGISel::selectScalarFPAsInt(SDValue N, SDValue &Imm) {
MVT VT = CFP->getSimpleValueType(0);
- // Even if this FPImm requires an additional FNEG (i.e. the second element of
- // the returned pair is true) we still prefer FLI + FNEG over immediate
- // materialization as the latter might generate a longer instruction sequence.
- if (static_cast<const RISCVTargetLowering *>(TLI)->getLegalZfaFPImm(APF,
- VT) >= 0)
- return false;
-
MVT XLenVT = Subtarget->getXLenVT();
if (VT == MVT::f64 && !Subtarget->is64Bit()) {
assert(APF.isNegZero() && "Unexpected constant.");
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 189fb741f34cd1..fc12c88445200d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2268,9 +2268,6 @@ bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
if (!IsLegalVT)
return false;
- if (getLegalZfaFPImm(Imm, VT) >= 0)
- return true;
-
// Cannot create a 64 bit floating-point immediate value for rv32.
if (Subtarget.getXLen() < VT.getScalarSizeInBits()) {
// td can handle +0.0 or -0.0 already.
@@ -5802,22 +5799,29 @@ SDValue RISCVTargetLowering::lowerConstantFP(SDValue Op,
MVT VT = Op.getSimpleValueType();
const APFloat &Imm = cast<ConstantFPSDNode>(Op)->getValueAPF();
- if (getLegalZfaFPImm(Imm, VT) >= 0)
- return Op;
+ // Can this constant be select by a Zfa FLI instruction?
+ bool Negate = false;
+ int Index = getLegalZfaFPImm(Imm, VT);
- if (!Imm.isNegative())
- return SDValue();
+ // If the constant is negative, try negating.
+ if (Index < 0 && Imm.isNegative()) {
+ Index = getLegalZfaFPImm(-Imm, VT);
+ Negate = true;
+ }
- int Index = getLegalZfaFPImm(-Imm, VT);
+ // If we couldn't find a FLI lowering, fall back to generic code.
if (Index < 0)
return SDValue();
// Emit an FLI+FNEG. We use a custom node to hide from constant folding.
SDLoc DL(Op);
SDValue Const =
- DAG.getNode(RISCVISD::FLI, Op, VT,
+ DAG.getNode(RISCVISD::FLI, DL, VT,
DAG.getTargetConstant(Index, DL, Subtarget.getXLenVT()));
- return DAG.getNode(ISD::FNEG, Op, VT, Const);
+ if (!Negate)
+ return Const;
+
+ return DAG.getNode(ISD::FNEG, DL, VT, Const);
}
static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
|
dtcxzyw
added a commit
to dtcxzyw/llvm-codegen-benchmark
that referenced
this pull request
Sep 19, 2024
|
This patch is not NFC. Before: After: |
Thanks. I'll take look. |
dtcxzyw
added a commit
to dtcxzyw/llvm-codegen-benchmark
that referenced
this pull request
Sep 19, 2024
asb
approved these changes
Sep 19, 2024
| @@ -5802,22 +5802,29 @@ SDValue RISCVTargetLowering::lowerConstantFP(SDValue Op, | |||
| MVT VT = Op.getSimpleValueType(); | |||
| const APFloat &Imm = cast<ConstantFPSDNode>(Op)->getValueAPF(); | |||
|
|
|||
| if (getLegalZfaFPImm(Imm, VT) >= 0) | |||
| return Op; | |||
| // Can this constant be select by a Zfa FLI instruction? | |||
There was a problem hiding this comment.
Tiny nit: "select" -> "selected"
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/134/builds/5612 Here is the relevant piece of the build log for the reference |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
We already moved the fneg case. This moves the rest so we can drop the custom isel.