[AMDGPU][MC] Instructions not to be supported in GFX940

[jwanggit86]

Buffer_store_lds_dword, buffer_wbinvl1, and buffer_wbinvl1_vol are obsolete in GFX940 and should not be supported.

[llvmbot]

@llvm/pr-subscribers-backend-amdgpu

@llvm/pr-subscribers-mc

Author: Jun Wang (jwanggit86)

Changes

Buffer_store_lds_dword, buffer_wbinvl1, and buffer_wbinvl1_vol are obsolete in GFX940 and should not be supported.

---

Full diff: https://github.com/llvm/llvm-project/pull/109225.diff

5 Files Affected:

• (modified) llvm/lib/Target/AMDGPU/BUFInstructions.td (+9-3)
• (modified) llvm/test/MC/AMDGPU/gfx10_unsupported.s (+3)
• (modified) llvm/test/MC/AMDGPU/gfx11_unsupported.s (+3)
• (modified) llvm/test/MC/AMDGPU/gfx12_unsupported.s (+6)
• (added) llvm/test/MC/AMDGPU/gfx940_unsupported.s (+11)

diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td
index c6668b24f4ef67..1bc5cd140f14ec 100644
--- a/llvm/lib/Target/AMDGPU/BUFInstructions.td
+++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td
@@ -3277,12 +3277,18 @@ defm BUFFER_ATOMIC_XOR_X2       : MUBUF_Real_Atomic_vi <0x6a>;
 defm BUFFER_ATOMIC_INC_X2       : MUBUF_Real_Atomic_vi <0x6b>;
 defm BUFFER_ATOMIC_DEC_X2       : MUBUF_Real_Atomic_vi <0x6c>;
 
-defm BUFFER_STORE_LDS_DWORD     : MUBUF_Real_vi_gfx90a <0x3d>;
+let AssemblerPredicate = isGFX8GFX9NotGFX90A in {
+defm BUFFER_STORE_LDS_DWORD     : MUBUF_Real_vi <0x3d>;
+}
+
+let AssemblerPredicate = isGFX90AOnly in {
+defm BUFFER_STORE_LDS_DWORD     : MUBUF_Real_gfx90a <0x3d>;
+}
 
-let AssemblerPredicate = isGFX8GFX9 in {
+let AssemblerPredicate = isGFX8GFX9NotGFX940 in {
 defm BUFFER_WBINVL1             : MUBUF_Real_vi <0x3e>;
 defm BUFFER_WBINVL1_VOL         : MUBUF_Real_vi <0x3f>;
-} // End AssemblerPredicate = isGFX8GFX9
+} // End AssemblerPredicate = isGFX8GFX9NotGFX940
 
 
 defm BUFFER_ATOMIC_PK_ADD_F16 : MUBUF_Real_Atomic_vi <0x4e>;
diff --git a/llvm/test/MC/AMDGPU/gfx10_unsupported.s b/llvm/test/MC/AMDGPU/gfx10_unsupported.s
index 1374417ac354b3..5a9f382d334ee4 100644
--- a/llvm/test/MC/AMDGPU/gfx10_unsupported.s
+++ b/llvm/test/MC/AMDGPU/gfx10_unsupported.s
@@ -215,6 +215,9 @@ buffer_store_d16_hi_format_x v1, off, s[12:15], -1 offset:4095
 buffer_store_lds_dword s[4:7], -1 offset:4095 lds
 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
+buffer_wbinvl1
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
 buffer_wbinvl1_vol
 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
diff --git a/llvm/test/MC/AMDGPU/gfx11_unsupported.s b/llvm/test/MC/AMDGPU/gfx11_unsupported.s
index 1e8d7684e942a6..c9756a068890e7 100644
--- a/llvm/test/MC/AMDGPU/gfx11_unsupported.s
+++ b/llvm/test/MC/AMDGPU/gfx11_unsupported.s
@@ -34,6 +34,9 @@ buffer_invl2
 buffer_store_lds_dword s[4:7], -1 offset:4095 lds
 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
+buffer_wbinvl1
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
 buffer_wbinvl1_vol
 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
diff --git a/llvm/test/MC/AMDGPU/gfx12_unsupported.s b/llvm/test/MC/AMDGPU/gfx12_unsupported.s
index f0debbf052bcc1..c34cb9e29c1994 100644
--- a/llvm/test/MC/AMDGPU/gfx12_unsupported.s
+++ b/llvm/test/MC/AMDGPU/gfx12_unsupported.s
@@ -232,9 +232,15 @@ buffer_gl0_inv
 buffer_gl1_inv
 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
+buffer_store_lds_dword s[4:7], -1 offset:4095 lds
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
 buffer_wbinvl1
 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
+buffer_wbinvl1_vol
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
 flat_atomic_csub v1, v[0:1], v2 offset:64 th:TH_ATOMIC_RETURN
 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid instruction
 
diff --git a/llvm/test/MC/AMDGPU/gfx940_unsupported.s b/llvm/test/MC/AMDGPU/gfx940_unsupported.s
new file mode 100644
index 00000000000000..4ef53c7d952394
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx940_unsupported.s
@@ -0,0 +1,11 @@
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx940 %s 2>&1 | FileCheck --check-prefixes=CHECK --implicit-check-not=error: %s
+
+buffer_store_lds_dword s[4:7], -1 offset:4095 lds
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
+buffer_wbinvl1
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
+buffer_wbinvl1_vol
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+

[arsenm]

Are BUFFER_WBL2 and BUFFER_INVL2 also removed and mishandled?

[arsenm]

You generally shouldn't need to touch AssemblerPredicate. The SubtargetPredicate on the pseudodefintion is wrong, should fix it there.

[jwanggit86]

Are BUFFER_WBL2 and BUFFER_INVL2 also removed and mishandled?

Based on the ISA doc, buffer_wbl2 is supported in GFX940, while buffer_invl2 is not. Sp3, however, allows buffer_invl2 for GFX940.

[arsenm]

Sp3, however, allows buffer_invl2 for GFX940.

This sounds more like an sp3 bug

[arsenm]

lgtm but I think we should add more subtarget features instead of these increasingly complex generation checks

[arsenm]

These clumsy subtarget checks should really be replaced with a subtarget feature