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[mlir][vector][nfc] Update vector load/store doc wrt unit strides. #109267

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Merged
merged 3 commits into from
Sep 19, 2024

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Hardcode84
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Follow up to #108998.

Non-contiguous strides are allowed now for 1-element vector load/stores.

Follow up to llvm#108998.

Non-contigious strides are allowed for 1-slement vector load/stores.
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llvmbot commented Sep 19, 2024

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Author: Ivan Butygin (Hardcode84)

Changes

Follow up to #108998.

Non-contiguous strides are allowed now for 1-element vector load/stores.


Full diff: https://github.com/llvm/llvm-project/pull/109267.diff

1 Files Affected:

  • (modified) mlir/include/mlir/Dialect/Vector/IR/VectorOps.td (+2)
diff --git a/mlir/include/mlir/Dialect/Vector/IR/VectorOps.td b/mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
index b96f5c2651bce5..65ed9b9d3df927 100644
--- a/mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
+++ b/mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
@@ -1655,6 +1655,7 @@ def Vector_LoadOp : Vector_Op<"load"> {
     strides. Only unit strides are allowed along the most minor memref
     dimension. These constraints guarantee that elements read along the first
     dimension of the slice are contiguous in memory.
+    Non-unit strides are allowed when doing 0-rank or 1-element vector load.
 
     The memref element type can be a scalar or a vector type. If the memref
     element type is a scalar, it should match the element type of the result
@@ -1739,6 +1740,7 @@ def Vector_StoreOp : Vector_Op<"store"> {
     strided by the memref strides. Only unit strides are allowed along the most
     minor memref dimension. These constraints guarantee that elements written
     along the first dimension of the slice are contiguous in memory.
+    Non-unit strides are allowed when doing 0-rank or 1-element vector store.
 
     The memref element type can be a scalar or a vector type. If the memref
     element type is a scalar, it should match the element type of the value

@Hardcode84 Hardcode84 changed the title [mlir][vector] Update vector load/store doc wrt unit strides. [mlir][vector][nfc] Update vector load/store doc wrt unit strides. Sep 19, 2024
Comment on lines 1655 to 1658
strides. Only unit strides are allowed along the most minor memref
dimension. These constraints guarantee that elements read along the first
dimension of the slice are contiguous in memory.
Non-unit strides are allowed when doing 0-rank or 1-element vector load.
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[nit]

Suggested change
strides. Only unit strides are allowed along the most minor memref
dimension. These constraints guarantee that elements read along the first
dimension of the slice are contiguous in memory.
Non-unit strides are allowed when doing 0-rank or 1-element vector load.
strides. When loading more than 1 element, only unit strides are allowed along the most minor memref
dimension. These constraints guarantee that elements read along the first
dimension of the slice are contiguous in memory.

Rather than adding a sentence at the end (and splitting one condition across multiple sentences), why not just refine the current wording? Hope I'm not splitting hairs here 😅

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yeah, that's better, probably.

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LGTM, thanks!

@Hardcode84 Hardcode84 merged commit 96ac627 into llvm:main Sep 19, 2024
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@Hardcode84 Hardcode84 deleted the vector-update-doc branch September 19, 2024 11:52
tmsri pushed a commit to tmsri/llvm-project that referenced this pull request Sep 19, 2024
…lvm#109267)

Follow up to llvm#108998.

Non-contiguous strides are allowed now for 1-element vector load/stores.
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3 participants