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[ARM] Fix VMOVRRD combine with non-canonical inserts. #109639

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Merged
merged 1 commit into from
Sep 24, 2024
Merged

[ARM] Fix VMOVRRD combine with non-canonical inserts. #109639

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4 changes: 2 additions & 2 deletions llvm/lib/Target/ARM/ARMISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -15131,9 +15131,9 @@ static SDValue PerformVMOVRRDCombine(SDNode *N,
SDValue Op0, Op1;
while (BV.getOpcode() == ISD::INSERT_VECTOR_ELT) {
if (isa<ConstantSDNode>(BV.getOperand(2))) {
if (BV.getConstantOperandVal(2) == Offset)
if (BV.getConstantOperandVal(2) == Offset && !Op0)
Op0 = BV.getOperand(1);
if (BV.getConstantOperandVal(2) == Offset + 1)
if (BV.getConstantOperandVal(2) == Offset + 1 && !Op1)
Op1 = BV.getOperand(1);
}
BV = BV.getOperand(0);
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66 changes: 66 additions & 0 deletions llvm/test/CodeGen/Thumb2/mve-soft-float-abi.ll
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Expand Up @@ -543,3 +543,69 @@ define <4 x i32> @insertextract(i32 %x, i32 %y) {
%4 = insertelement <4 x i32> %3, i32 %y, i32 3
ret <4 x i32> %4
}

declare void @print_uint32x4_t(<4 x i32> %val)
define i32 @main(i64 %x, i64 %y) {
; CHECK-LE-LABEL: main:
; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: .save {r4, lr}
; CHECK-LE-NEXT: push {r4, lr}
; CHECK-LE-NEXT: .vsave {d8, d9}
; CHECK-LE-NEXT: vpush {d8, d9}
; CHECK-LE-NEXT: .pad #8
; CHECK-LE-NEXT: sub sp, #8
; CHECK-LE-NEXT: vmov.32 q4[2], r2
; CHECK-LE-NEXT: mov r4, r1
; CHECK-LE-NEXT: mov r1, r0
; CHECK-LE-NEXT: vmov.32 q4[3], r3
; CHECK-LE-NEXT: movs r0, #0
; CHECK-LE-NEXT: mov r2, r1
; CHECK-LE-NEXT: mov r3, r4
; CHECK-LE-NEXT: vstr d9, [sp]
; CHECK-LE-NEXT: bl print_uint32x4_t
; CHECK-LE-NEXT: movs r0, #0
; CHECK-LE-NEXT: movs r2, #1
; CHECK-LE-NEXT: mov r3, r4
; CHECK-LE-NEXT: vstr d9, [sp]
; CHECK-LE-NEXT: bl print_uint32x4_t
; CHECK-LE-NEXT: movs r0, #0
; CHECK-LE-NEXT: add sp, #8
; CHECK-LE-NEXT: vpop {d8, d9}
; CHECK-LE-NEXT: pop {r4, pc}
;
; CHECK-BE-LABEL: main:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: .save {r4, lr}
; CHECK-BE-NEXT: push {r4, lr}
; CHECK-BE-NEXT: .vsave {d8, d9}
; CHECK-BE-NEXT: vpush {d8, d9}
; CHECK-BE-NEXT: .pad #8
; CHECK-BE-NEXT: sub sp, #8
; CHECK-BE-NEXT: vmov.32 q0[2], r2
; CHECK-BE-NEXT: mov r4, r1
; CHECK-BE-NEXT: mov r1, r0
; CHECK-BE-NEXT: vmov.32 q0[3], r3
; CHECK-BE-NEXT: vrev64.32 q4, q0
; CHECK-BE-NEXT: movs r0, #0
; CHECK-BE-NEXT: mov r2, r1
; CHECK-BE-NEXT: mov r3, r4
; CHECK-BE-NEXT: vstr d9, [sp]
; CHECK-BE-NEXT: bl print_uint32x4_t
; CHECK-BE-NEXT: movs r0, #0
; CHECK-BE-NEXT: movs r2, #1
; CHECK-BE-NEXT: mov r3, r4
; CHECK-BE-NEXT: vstr d9, [sp]
; CHECK-BE-NEXT: bl print_uint32x4_t
; CHECK-BE-NEXT: movs r0, #0
; CHECK-BE-NEXT: add sp, #8
; CHECK-BE-NEXT: vpop {d8, d9}
; CHECK-BE-NEXT: pop {r4, pc}
entry:
%a = insertelement <2 x i64> poison, i64 %x, i64 0
%b = insertelement <2 x i64> %a, i64 %y, i64 1
%c = bitcast <2 x i64> %b to <4 x i32>
%i = insertelement <4 x i32> %c, i32 1, i64 0
tail call void @print_uint32x4_t(i32 0, <4 x i32> %c)
tail call void @print_uint32x4_t(i32 0, <4 x i32> %i)
ret i32 0
}
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