llvm-reduce: Don't print verifier failed machine functions #109673
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This produces far too much terminal output, particularly for the instruction reduction. Since it doesn't consider the liveness of of the instructions it's deleting, it produces quite a lot of verifier errors.
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LGTM, unless this wants a test on it |
aeubanks
reviewed
Sep 23, 2024
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or to match the LLVM IR verifier more, a |
qcolombet
approved these changes
Sep 23, 2024
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@llvm/pr-subscribers-llvm-regalloc Author: Matt Arsenault (arsenm) ChangesThis produces far too much terminal output, particularly for the Patch is 32.82 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/109673.diff 9 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h
index aeb72ca24d79b8..5c1da4fa762e84 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -897,13 +897,14 @@ class LLVM_ABI MachineFunction {
/// for debugger use.
/// \returns true if no problems were found.
bool verify(Pass *p = nullptr, const char *Banner = nullptr,
- bool AbortOnError = true) const;
+ raw_ostream *OS = nullptr, bool AbortOnError = true) const;
/// Run the current MachineFunction through the machine code verifier, useful
/// for debugger use.
/// \returns true if no problems were found.
bool verify(LiveIntervals *LiveInts, SlotIndexes *Indexes,
- const char *Banner = nullptr, bool AbortOnError = true) const;
+ const char *Banner = nullptr, raw_ostream *OS = nullptr,
+ bool AbortOnError = true) const;
// Provide accessors for the MachineBasicBlock list...
using iterator = BasicBlockListType::iterator;
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index d506cd1879648f..947344e3ea775c 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -604,7 +604,7 @@ MIRParserImpl::initializeMachineFunction(const yaml::MachineFunction &YamlMF,
MF.getSubtarget().mirFileLoaded(MF);
- MF.verify();
+ MF.verify(nullptr, nullptr, &errs());
return false;
}
diff --git a/llvm/lib/CodeGen/MachineBlockPlacement.cpp b/llvm/lib/CodeGen/MachineBlockPlacement.cpp
index be783bc4e29738..99254c710b3012 100644
--- a/llvm/lib/CodeGen/MachineBlockPlacement.cpp
+++ b/llvm/lib/CodeGen/MachineBlockPlacement.cpp
@@ -3705,7 +3705,7 @@ void MachineBlockPlacement::assignBlockOrder(
#ifndef NDEBUG
// Make sure we correctly constructed all branches.
- F->verify(this, "After optimized block reordering");
+ F->verify(this, "After optimized block reordering", &errs());
#endif
}
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 4e6d34346b1d80..9b2862de22b690 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -453,7 +453,7 @@ bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
if (VerifyScheduling) {
LLVM_DEBUG(LIS->dump());
- MF->verify(this, "Before machine scheduling.");
+ MF->verify(this, "Before machine scheduling.", &errs());
}
RegClassInfo->runOnMachineFunction(*MF);
@@ -472,7 +472,7 @@ bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
LLVM_DEBUG(LIS->dump());
if (VerifyScheduling)
- MF->verify(this, "After machine scheduling.");
+ MF->verify(this, "After machine scheduling.", &errs());
return true;
}
@@ -496,7 +496,7 @@ bool PostMachineScheduler::runOnMachineFunction(MachineFunction &mf) {
AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
if (VerifyScheduling)
- MF->verify(this, "Before post machine scheduling.");
+ MF->verify(this, "Before post machine scheduling.", &errs());
// Instantiate the selected scheduler for this target, function, and
// optimization level.
@@ -512,7 +512,7 @@ bool PostMachineScheduler::runOnMachineFunction(MachineFunction &mf) {
scheduleRegions(*Scheduler, true);
if (VerifyScheduling)
- MF->verify(this, "After post machine scheduling.");
+ MF->verify(this, "After post machine scheduling.", &errs());
return true;
}
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 27664207d1e696..359cf04034ecab 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -94,21 +94,24 @@ using namespace llvm;
namespace {
struct MachineVerifier {
- MachineVerifier(MachineFunctionAnalysisManager &MFAM, const char *b)
- : MFAM(&MFAM), Banner(b) {}
+ MachineVerifier(MachineFunctionAnalysisManager &MFAM, const char *b,
+ raw_ostream *OS)
+ : MFAM(&MFAM), OS(OS ? OS : &nulls()), Banner(b) {}
- MachineVerifier(Pass *pass, const char *b) : PASS(pass), Banner(b) {}
+ MachineVerifier(Pass *pass, const char *b, raw_ostream *OS)
+ : PASS(pass), OS(OS ? OS : &nulls()), Banner(b) {}
MachineVerifier(const char *b, LiveVariables *LiveVars,
LiveIntervals *LiveInts, LiveStacks *LiveStks,
- SlotIndexes *Indexes)
- : Banner(b), LiveVars(LiveVars), LiveInts(LiveInts), LiveStks(LiveStks),
- Indexes(Indexes) {}
+ SlotIndexes *Indexes, raw_ostream *OS)
+ : OS(OS ? OS : &nulls()), Banner(b), LiveVars(LiveVars),
+ LiveInts(LiveInts), LiveStks(LiveStks), Indexes(Indexes) {}
unsigned verify(const MachineFunction &MF);
MachineFunctionAnalysisManager *MFAM = nullptr;
Pass *const PASS = nullptr;
+ raw_ostream *OS = nullptr;
const char *Banner;
const MachineFunction *MF = nullptr;
const TargetMachine *TM = nullptr;
@@ -334,7 +337,8 @@ namespace {
MachineFunctionProperties::Property::FailsVerification))
return false;
- unsigned FoundErrors = MachineVerifier(this, Banner.c_str()).verify(MF);
+ unsigned FoundErrors =
+ MachineVerifier(this, Banner.c_str(), &errs()).verify(MF);
if (FoundErrors)
report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
return false;
@@ -352,7 +356,8 @@ MachineVerifierPass::run(MachineFunction &MF,
if (MF.getProperties().hasProperty(
MachineFunctionProperties::Property::FailsVerification))
return PreservedAnalyses::all();
- unsigned FoundErrors = MachineVerifier(MFAM, Banner.c_str()).verify(MF);
+ unsigned FoundErrors =
+ MachineVerifier(MFAM, Banner.c_str(), &errs()).verify(MF);
if (FoundErrors)
report_fatal_error("Found " + Twine(FoundErrors) + " machine code errors.");
return PreservedAnalyses::all();
@@ -374,25 +379,28 @@ void llvm::verifyMachineFunction(const std::string &Banner,
// LiveIntervals *LiveInts;
// LiveStacks *LiveStks;
// SlotIndexes *Indexes;
- unsigned FoundErrors = MachineVerifier(nullptr, Banner.c_str()).verify(MF);
+ unsigned FoundErrors =
+ MachineVerifier(nullptr, Banner.c_str(), &errs()).verify(MF);
if (FoundErrors)
report_fatal_error("Found " + Twine(FoundErrors) + " machine code errors.");
}
-bool MachineFunction::verify(Pass *p, const char *Banner, bool AbortOnErrors)
- const {
+bool MachineFunction::verify(Pass *p, const char *Banner, raw_ostream *OS,
+ bool AbortOnErrors) const {
MachineFunction &MF = const_cast<MachineFunction&>(*this);
- unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
+ unsigned FoundErrors = MachineVerifier(p, Banner, OS).verify(MF);
if (AbortOnErrors && FoundErrors)
report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
return FoundErrors == 0;
}
bool MachineFunction::verify(LiveIntervals *LiveInts, SlotIndexes *Indexes,
- const char *Banner, bool AbortOnErrors) const {
+ const char *Banner, raw_ostream *OS,
+ bool AbortOnErrors) const {
MachineFunction &MF = const_cast<MachineFunction &>(*this);
unsigned FoundErrors =
- MachineVerifier(Banner, nullptr, LiveInts, nullptr, Indexes).verify(MF);
+ MachineVerifier(Banner, nullptr, LiveInts, nullptr, Indexes, OS)
+ .verify(MF);
if (AbortOnErrors && FoundErrors)
report_fatal_error("Found " + Twine(FoundErrors) + " machine code errors.");
return FoundErrors == 0;
@@ -482,7 +490,7 @@ unsigned MachineVerifier::verify(const MachineFunction &MF) {
for (const MachineInstr &MI : MBB.instrs()) {
if (MI.getParent() != &MBB) {
report("Bad instruction parent pointer", &MBB);
- errs() << "Instruction: " << MI;
+ *OS << "Instruction: " << MI;
continue;
}
@@ -540,46 +548,48 @@ unsigned MachineVerifier::verify(const MachineFunction &MF) {
void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
assert(MF);
- errs() << '\n';
+ *OS << '\n';
if (!foundErrors++) {
if (Banner)
- errs() << "# " << Banner << '\n';
+ *OS << "# " << Banner << '\n';
+
if (LiveInts != nullptr)
- LiveInts->print(errs());
+ LiveInts->print(*OS);
else
- MF->print(errs(), Indexes);
+ MF->print(*OS, Indexes);
}
- errs() << "*** Bad machine code: " << msg << " ***\n"
- << "- function: " << MF->getName() << "\n";
+
+ *OS << "*** Bad machine code: " << msg << " ***\n"
+ << "- function: " << MF->getName() << '\n';
}
void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
assert(MBB);
report(msg, MBB->getParent());
- errs() << "- basic block: " << printMBBReference(*MBB) << ' '
- << MBB->getName() << " (" << (const void *)MBB << ')';
+ *OS << "- basic block: " << printMBBReference(*MBB) << ' ' << MBB->getName()
+ << " (" << (const void *)MBB << ')';
if (Indexes)
- errs() << " [" << Indexes->getMBBStartIdx(MBB)
- << ';' << Indexes->getMBBEndIdx(MBB) << ')';
- errs() << '\n';
+ *OS << " [" << Indexes->getMBBStartIdx(MBB) << ';'
+ << Indexes->getMBBEndIdx(MBB) << ')';
+ *OS << '\n';
}
void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
assert(MI);
report(msg, MI->getParent());
- errs() << "- instruction: ";
+ *OS << "- instruction: ";
if (Indexes && Indexes->hasIndex(*MI))
- errs() << Indexes->getInstructionIndex(*MI) << '\t';
- MI->print(errs(), /*IsStandalone=*/true);
+ *OS << Indexes->getInstructionIndex(*MI) << '\t';
+ MI->print(*OS, /*IsStandalone=*/true);
}
void MachineVerifier::report(const char *msg, const MachineOperand *MO,
unsigned MONum, LLT MOVRegType) {
assert(MO);
report(msg, MO->getParent());
- errs() << "- operand " << MONum << ": ";
- MO->print(errs(), MOVRegType, TRI);
- errs() << "\n";
+ *OS << "- operand " << MONum << ": ";
+ MO->print(*OS, MOVRegType, TRI);
+ *OS << '\n';
}
void MachineVerifier::report(const Twine &Msg, const MachineInstr *MI) {
@@ -587,11 +597,11 @@ void MachineVerifier::report(const Twine &Msg, const MachineInstr *MI) {
}
void MachineVerifier::report_context(SlotIndex Pos) const {
- errs() << "- at: " << Pos << '\n';
+ *OS << "- at: " << Pos << '\n';
}
void MachineVerifier::report_context(const LiveInterval &LI) const {
- errs() << "- interval: " << LI << '\n';
+ *OS << "- interval: " << LI << '\n';
}
void MachineVerifier::report_context(const LiveRange &LR, Register VRegUnit,
@@ -603,35 +613,35 @@ void MachineVerifier::report_context(const LiveRange &LR, Register VRegUnit,
}
void MachineVerifier::report_context(const LiveRange::Segment &S) const {
- errs() << "- segment: " << S << '\n';
+ *OS << "- segment: " << S << '\n';
}
void MachineVerifier::report_context(const VNInfo &VNI) const {
- errs() << "- ValNo: " << VNI.id << " (def " << VNI.def << ")\n";
+ *OS << "- ValNo: " << VNI.id << " (def " << VNI.def << ")\n";
}
void MachineVerifier::report_context_liverange(const LiveRange &LR) const {
- errs() << "- liverange: " << LR << '\n';
+ *OS << "- liverange: " << LR << '\n';
}
void MachineVerifier::report_context(MCPhysReg PReg) const {
- errs() << "- p. register: " << printReg(PReg, TRI) << '\n';
+ *OS << "- p. register: " << printReg(PReg, TRI) << '\n';
}
void MachineVerifier::report_context_vreg(Register VReg) const {
- errs() << "- v. register: " << printReg(VReg, TRI) << '\n';
+ *OS << "- v. register: " << printReg(VReg, TRI) << '\n';
}
void MachineVerifier::report_context_vreg_regunit(Register VRegOrUnit) const {
if (VRegOrUnit.isVirtual()) {
report_context_vreg(VRegOrUnit);
} else {
- errs() << "- regunit: " << printRegUnit(VRegOrUnit, TRI) << '\n';
+ *OS << "- regunit: " << printRegUnit(VRegOrUnit, TRI) << '\n';
}
}
void MachineVerifier::report_context_lanemask(LaneBitmask LaneMask) const {
- errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
+ *OS << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
}
void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
@@ -710,8 +720,8 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
report("MBB has successor that isn't part of the function.", MBB);
if (!MBBInfoMap[succ].Preds.count(MBB)) {
report("Inconsistent CFG", MBB);
- errs() << "MBB is not in the predecessor list of the successor "
- << printMBBReference(*succ) << ".\n";
+ *OS << "MBB is not in the predecessor list of the successor "
+ << printMBBReference(*succ) << ".\n";
}
}
@@ -721,8 +731,8 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
report("MBB has predecessor that isn't part of the function.", MBB);
if (!MBBInfoMap[Pred].Succs.count(MBB)) {
report("Inconsistent CFG", MBB);
- errs() << "MBB is not in the successor list of the predecessor "
- << printMBBReference(*Pred) << ".\n";
+ *OS << "MBB is not in the successor list of the predecessor "
+ << printMBBReference(*Pred) << ".\n";
}
}
@@ -880,7 +890,7 @@ void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
SlotIndex idx = Indexes->getInstructionIndex(*MI);
if (!(idx > lastIndex)) {
report("Instruction index out of order", MI);
- errs() << "Last instruction was at " << lastIndex << '\n';
+ *OS << "Last instruction was at " << lastIndex << '\n';
}
lastIndex = idx;
}
@@ -894,7 +904,7 @@ void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
// precede non-terminators.
if (FirstTerminator->getOpcode() != TargetOpcode::G_INVOKE_REGION_START) {
report("Non-terminator instruction after the first terminator", MI);
- errs() << "First terminator was:\t" << *FirstTerminator;
+ *OS << "First terminator was:\t" << *FirstTerminator;
}
}
}
@@ -2185,8 +2195,8 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
const MCInstrDesc &MCID = MI->getDesc();
if (MI->getNumOperands() < MCID.getNumOperands()) {
report("Too few operands", MI);
- errs() << MCID.getNumOperands() << " operands expected, but "
- << MI->getNumOperands() << " given.\n";
+ *OS << MCID.getNumOperands() << " operands expected, but "
+ << MI->getNumOperands() << " given.\n";
}
if (MI->getFlag(MachineInstr::NoConvergent) && !MCID.isConvergent())
@@ -2278,7 +2288,7 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
// If both types are valid, check that the types are the same.
if (SrcTy != DstTy) {
report("Copy Instruction is illegal with mismatching types", MI);
- errs() << "Def = " << DstTy << ", Src = " << SrcTy << "\n";
+ *OS << "Def = " << DstTy << ", Src = " << SrcTy << '\n';
}
break;
@@ -2322,8 +2332,7 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
if (SrcSize.isNonZero() && DstSize.isNonZero() && SrcSize != DstSize) {
if (!DstOp.getSubReg() && !SrcOp.getSubReg()) {
report("Copy Instruction is illegal with mismatching sizes", MI);
- errs() << "Def Size = " << DstSize << ", Src Size = " << SrcSize
- << "\n";
+ *OS << "Def Size = " << DstSize << ", Src Size = " << SrcSize << '\n';
}
}
break;
@@ -2554,8 +2563,8 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
TII->getRegClass(MCID, MONum, TRI, *MF)) {
if (!DRC->contains(Reg)) {
report("Illegal physical register for instruction", MO, MONum);
- errs() << printReg(Reg, TRI) << " is not a "
- << TRI->getRegClassName(DRC) << " register.\n";
+ *OS << printReg(Reg, TRI) << " is not a "
+ << TRI->getRegClassName(DRC) << " register.\n";
}
}
}
@@ -2618,9 +2627,9 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
RBI->getMaximumSize(RegBank->getID()) < Ty.getSizeInBits()) {
report("Register bank is too small for virtual register", MO,
MONum);
- errs() << "Register bank " << RegBank->getName() << " too small("
- << RBI->getMaximumSize(RegBank->getID()) << ") to fit "
- << Ty.getSizeInBits() << "-bits\n";
+ *OS << "Register bank " << RegBank->getName() << " too small("
+ << RBI->getMaximumSize(RegBank->getID()) << ") to fit "
+ << Ty.getSizeInBits() << "-bits\n";
return;
}
}
@@ -2639,10 +2648,9 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
TII->getRegClass(MCID, MONum, TRI, *MF)) {
report("Virtual register does not match instruction constraint", MO,
MONum);
- errs() << "Expect register class "
- << TRI->getRegClassName(
- TII->getRegClass(MCID, MONum, TRI, *MF))
- << " but got nothing\n";
+ *OS << "Expect register class "
+ << TRI->getRegClassName(TII->getRegClass(MCID, MONum, TRI, *MF))
+ << " but got nothing\n";
return;
}
@@ -2653,14 +2661,14 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
TRI->getSubClassWithSubReg(RC, SubIdx);
if (!SRC) {
report("Invalid subregister index for virtual register", MO, MONum);
- errs() << "Register class " << TRI->getRegClassName(RC)
- << " does not support subreg index " << SubIdx << "\n";
+ *OS << "Register class " << TRI->getRegClassName(RC)
+ << " does not support subreg index " << SubIdx << '\n';
return;
}
if (RC != SRC) {
report("Invalid register class for subregister index", MO, MONum);
- errs() << "Register class " << TRI->getRegClassName(RC)
- << " does not fully support subreg index " << SubIdx << "\n";
+ *OS << "Register class " << TRI->getRegClassName(RC)
+ << " does not fully support subreg index " << SubIdx << '\n';
return;
}
}
@@ -2682,7 +2690,7 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
}
if (!RC->hasSuperClassEq(DRC)) {
report("Illegal virtual register for instruction", MO, MONum);
- errs() << "Expected a " << TRI->getRegClassName(DRC)
+ *OS << "Expected a " << TRI->getRegClassName(DRC)
<< " register, but got a " << TRI->getRegClassName(RC)
<< " register\n";
}
@@ -2733,11 +2741,11 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
}
if (loads && !LI.liveAt(Idx.getRegSlot(true))) {
report("Instruction loads from dead spill slot", MO, MONum);
- errs() << "Live stack: " << LI << '\n';
+ *OS << "Live stack: " << LI << '\n';
}
if (stores && !LI.liveAt(Idx.getRegSlot())) {
report("Instruction stores to dead spill slot", MO, MONum);
- errs() << "Live stack: " << LI << '\n';
+ *OS << "Live stack: " << LI << '\n';
}
}
break;
@@ -3032,8 +3040,8 @@ MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
SlotIndex stop = Indexes->getMBBEndIdx(MBB);
if (!(stop > lastIndex)) {
report("Block ends before last instruction index", MBB);
- errs() << "Block ends at " << stop
- << " last instruction was at " << lastIndex << '\n';
+ *OS << "Block ends at " << stop << " last instruction was at "
+ << lastIndex << '\n';
}
lastIndex = stop;
}
@@ -3278,8 +3286,8 @@ void MachineVerifier::checkPHIOps(const MachineBasicBlock &MBB) {
for...
[truncated]
|
aeubanks
approved these changes
Sep 23, 2024
…d-machine-function
arsenm
deleted the
users/arsenm/llvm-reduce/stop-printing-failed-machine-function
branch
|
I noticed that if I run llc now, some input that previously failed in the calls in Is this expected? The commit message only talks about reducing output for llvm-reduce? |
This needs to pass in the output stream to the verify call, the default is now no output
I'm actually trying to remove all the fatal errors from LiveRangeCalc but not sure when I'll finish it |
Done in b7b945b |
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This produces far too much terminal output, particularly for the
instruction reduction. Since it doesn't consider the liveness of of
the instructions it's deleting, it produces quite a lot of verifier
errors.