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[RISCV] Don't create insert/extract subreg during lowering. #109754

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Merged
merged 2 commits into from
Sep 24, 2024
Merged

[RISCV] Don't create insert/extract subreg during lowering. #109754

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ee51d59
[RISCV] Don't create insert/extract subreg during lowering.
topperc Sep 24, 2024
6c65e6b
fixup! add assert.
topperc Sep 24, 2024
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27 changes: 22 additions & 5 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -10304,8 +10304,12 @@ SDValue RISCVTargetLowering::lowerINSERT_SUBVECTOR(SDValue Op,
return Op;
}

// Use a insert_subvector that will resolve to an insert subreg.
assert(VLen);
unsigned Vscale = *VLen / RISCV::RVVBitsPerBlock;
SDValue Insert =
DAG.getTargetInsertSubreg(SubRegIdx, DL, ContainerVecVT, Vec, SubVec);
DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ContainerVecVT, Vec, SubVec,
DAG.getConstant(OrigIdx / Vscale, DL, XLenVT));
if (VecVT.isFixedLengthVector())
Insert = convertFromScalableVector(VecVT, Insert, DAG, Subtarget);
return Insert;
Expand All @@ -10321,8 +10325,10 @@ SDValue RISCVTargetLowering::lowerINSERT_SUBVECTOR(SDValue Op,
MVT InterSubVT = ContainerVecVT;
SDValue AlignedExtract = Vec;
unsigned AlignedIdx = OrigIdx - RemIdx.getKnownMinValue();
if (SubVecVT.isFixedLengthVector())
if (SubVecVT.isFixedLengthVector()) {
assert(VLen);
AlignedIdx /= *VLen / RISCV::RVVBitsPerBlock;
}
if (ContainerVecVT.bitsGT(getLMUL1VT(ContainerVecVT))) {
InterSubVT = getLMUL1VT(ContainerVecVT);
// Extract a subvector equal to the nearest full vector register type. This
Expand Down Expand Up @@ -10499,10 +10505,14 @@ SDValue RISCVTargetLowering::lowerEXTRACT_SUBVECTOR(SDValue Op,

// If the Idx has been completely eliminated then this is a subvector extract
// which naturally aligns to a vector register. These can easily be handled
// using subregister manipulation.
// using subregister manipulation. We use an extract_subvector that will
// resolve to an extract subreg.
if (RemIdx.isZero()) {
if (SubVecVT.isFixedLengthVector()) {
Vec = DAG.getTargetExtractSubreg(SubRegIdx, DL, ContainerSubVecVT, Vec);
assert(VLen);
unsigned Vscale = *VLen / RISCV::RVVBitsPerBlock;
Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ContainerSubVecVT, Vec,
DAG.getConstant(OrigIdx / Vscale, DL, XLenVT));
return convertFromScalableVector(SubVecVT, Vec, DAG, Subtarget);
}
return Op;
Expand All @@ -10520,9 +10530,16 @@ SDValue RISCVTargetLowering::lowerEXTRACT_SUBVECTOR(SDValue Op,
if (VecVT.bitsGT(getLMUL1VT(VecVT))) {
// If VecVT has an LMUL > 1, then SubVecVT should have a smaller LMUL, and
// we should have successfully decomposed the extract into a subregister.
// We use an extract_subvector that will resolve to a subreg extract.
assert(SubRegIdx != RISCV::NoSubRegister);
unsigned Idx = OrigIdx - RemIdx.getKnownMinValue();
if (SubVecVT.isFixedLengthVector()) {
assert(VLen);
Idx /= *VLen / RISCV::RVVBitsPerBlock;
}
InterSubVT = getLMUL1VT(VecVT);
Vec = DAG.getTargetExtractSubreg(SubRegIdx, DL, InterSubVT, Vec);
Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InterSubVT, Vec,
DAG.getConstant(Idx, DL, XLenVT));
}

// Slide this vector register down by the desired number of elements in order
Expand Down
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