[AMDGPU] Fix has_single_bit assertion for Mask in SIInstrInfo

[GeorgeWeb]

Convert the int64_t Mask to uint64_t for llvm::has_single_bit to compile.

[llvmbot]

@llvm/pr-subscribers-backend-amdgpu

Author: Georgi Mirazchiyski (GeorgeWeb)

Changes

Convert the int64_t Mask to uint64_t for llvm::has_single_bit to compile.

---

Full diff: https://github.com/llvm/llvm-project/pull/109785.diff

1 Files Affected:

• (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (+1-1)

diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index f5f367b2a4a7c6..9ad0b4c65e1d90 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -9793,7 +9793,7 @@ bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
 
     // A valid Mask is required to have a single bit set, hence a non-zero and
     // power-of-two value. This verifies that we will not do 64-bit shift below.
-    assert(llvm::has_single_bit(Mask) && "Invalid mask.");
+    assert(llvm::has_single_bit<uint64_t>(Mask) && "Invalid mask.");
     unsigned BitNo = llvm::countr_zero((uint64_t)Mask);
     if (IsSigned && BitNo == SrcSize - 1)
       return false;

[GeorgeWeb]

Fixes build failures caused from 6cfe6a6. (see #108416 (comment))

[jplehr]

Thanks for fix! (at least for our bots)