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[RISCV] Fold (fmv_x_h/w (load)) to an integer load. #109900

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Merged
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Sep 25, 2024
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[RISCV] Fold (fmv_x_h/w (load)) to an integer load. #109900

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11 changes: 11 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -16984,6 +16984,17 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
return Op0.getOperand(0);
}

if (ISD::isNormalLoad(Op0.getNode()) && Op0.hasOneUse() &&
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Is there something here preventing the load from having an offset? I think the answer is that the load must be a vector load, and that we don't have base+offset addressing for that form, but could you add an assert here to confirm the offset is zero?

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@topperc topperc Sep 25, 2024 •
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I think the offset field in LoadSDNodeonly is only used by pre/post inc/dec loads. RISC-V only uses for some THead extensions. ISD::isNormalLoad checks that the load isUnindexed() so the offset field should be undef.

The immediate offset for scalar loads is represented by a separate ADD node in the base pointer that we pattern match at isel.

cast<LoadSDNode>(Op0)->isSimple()) {
MVT IVT = MVT::getIntegerVT(Op0.getValueSizeInBits());
auto *LN0 = cast<LoadSDNode>(Op0);
SDValue Load =
DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT, LN0->getChain(),
LN0->getBasePtr(), IVT, LN0->getMemOperand());
DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), Load.getValue(1));
return Load;
}

// This is a target-specific version of a DAGCombine performed in
// DAGCombiner::visitBITCAST. It performs the equivalent of:
// fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
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